Invited Speakers and Topics

EPTC 2019 Invited Paper Details Download


Invited-01:  Manufacturing Technology Solution of Small Via for Heterogeneous Integration.

Dr Yasuhiro Morikawa, Manager,Ulvac Inc.

Here, Smart ICT (Information andCommunication Technology) in the 5G era such as “Cloud computing”, “Fog/Edgecomputing” , and Smart Functionalities such as Stand-alone Self-activatingMEMS/Sensors construct Smart Systems which enable IoT (Internet of Things), IoE(Internet of Everything) thus Smart Society. Therefore, high-density packagingtechnologies such as 2.nD, 3D packaging scheme basing on advanced substratepackage, WLP (wafer level package) / PLP (Panel level package) as high-densityorganic interposer (RDL: re-distribution layer), Si interposer and TSV (thoughsilicon via) technologies are among key technologies to satisfy therequirements from the semiconductor devices for 5G/AI (artificialintelligence), and real-time or low latency (< 1ms) devices as“Edge-computing”.  ULVAC has been continuously developingmanufacturing solution technologies to realize the heterogeneous integrationSiP by Fan-out (substrate package, WLP / PLP) packaging, Si interposer, TSV andalso EMI (Electromagnetic Interference) shielding. In this presentation,buildup multilayer, RDL/Interposer and TSV technologies solutions consisting ofplasma etching / ashing and PVD (Physical Vapor Deposition) sputtering to makethe high density interconnection package will be introduced.

 

 

Invited-02:  Market and Technology Trends of Advanced Packaging,Fan-Out Packaging

Mr Favier Shoo, Technology and MarketAnalyst, Yole Development

In this digital new age, advanced nodesdo not bring the desired cost-benefit anymore and R&D investments in newlithography solutions and devices below 10nm nodes are rising substantially.Hence, advanced packaging represents an opportunity to increase product valueoffering advantages down both the scaling and functional roadmaps. This presentationwill focus on arguably one of the most exciting advanced packaging platforms –Fan-Out Packaging. In 2019, key players from all different business models haveFan-Out packaging solutions in the market. Fan-out packaging technology is notonly a bridge to chip-package interaction (CPI) mismatch in pitch size, but isalso a viable solution for heterogeneous integration of functionalities, nowpotentially used for mmWave 5G and Cloud data server applications. Fan-outsuccess is evidently defined by the well-established “core” standard FO marketand the startling market penetration of high-density FO (HDFO), which broughtFan-Out Packaging into a whole new level of spotlight.

 

 

Invited-03:  Highly Accurate,Efficient and Reliable Silicon Photonics Wafer-Level Test and Characterization

Dr Sia Choon Beng, TechnicalConsultant, FormFactor Inc, Singapore

By 2030, to satisfy the increasingdemands for cloud computing and services for various emerging applications suchas artificial intelligence, genomics revolution and video transcoding etc, theenergy consumption of all data centers is projected to be about 20% of theearth’s total energy produced! Silicon photonics with optical fibers is thepotential candidate to replace copper interconnects within data centers as itdrastically reduce power consumption, cost and size of the optical transceivermodules. By utilising the mature silicon CMOS processing technologies,silicon-based photonics products can be fabricated cost-effectively withwell-established production solution. In this invited talk, an optimized andautomated setup for optoelectronic test and characterization will be presented.The setup is currently used for known-good-die tests prior to die stackingwhich is crucial for effective 3DIC heterogeneous integration and packaging ofsilicon-based optical transceivers. This talk also presents possible solutionsto establish challenging correlations of wafer-level tests to the final producttests - as most silicon photonics chips utilize edge couplers to transfer lightin and out of the chip in IC packages while most of the commercially availablewafer-level test solutions require grating couplers for wafer top-side lighttransfer.

 



Invited-04: Reduction of Aging InducedReliability Degradations Using SAC+X Lead Free Solders

Prof Jeffrey Suhling, Auburn University

Environmental concerns and legislationadopted in Europe and Asia has led to a nearly universal world-wide transitionto lead free solders in electronic products over the past 15years.  Most of the lead free solders in use are Sn-Ag-Cu (SAC)alloys.  One of the greatest challenges has been that SAC lead freesolders are highly susceptible to aging effects, where their mechanicalbehavior and failure properties degrade with time when exposed to isothermal orvariable temperature environments.  Such degradations are caused bythe unstable microstructures present at very low temperatures, and they canlead to a significant reduction in the reliability of electronic products withtime.

In this talk, an overview of ourresearch on the effects of aging on the mechanical behavior of lead freesolders is presented.  In particular, approaches for mitigating agingeffects through the use of additional alloying elements within the traditionalSAC alloys will be presented.  This work has involved a combinationof experimental material characterization and measurements of microstructuralevolution, as well as constitutive model development and finite elementpredictions of reliability.  Stress-strain and creep tests have beenperformed on SAC and SAC+X alloys using miniature tensile samples, and thedegradations in the effective elastic modulus, yield stress, ultimate tensilestrength, and creep strain rate have been characterized and modeled as afunction of aging temperature, aging time, and alloycomposition.  Analogous results have also been obtained usingnanoindentation testing of small solder joints from non-aged and aged lead freeelectronic assemblies.  Finally, cyclic stress-strain testing hasbeen utilized to understand the aging induced degradations in the hysteresisloop and fatigue life.

The results of the experimentalmechanical testing have been correlated with observations of microstructuralevolution occurring in the SAC and SAC+X lead free solders during aging todevelop a fundamental understanding of the causes of the material propertydegradations.  It was found that the coarsening of IMC particles wasgreatly mitigated in SAC+Bi alloys relative to those observed in thetraditional SAC alloys.  Immediately after reflow solidification,bismuth rich phases were present in the SAC+Bi joints.  During agingat T = 125 C, the bismuth was observed to quickly go into solution both withinthe beta-Sn dendrites and in the intermetallic rich regions betweendendrites.  This resulted in solid solution strengthening of the leadfree solder.  It was also found that the aging-induced presence ofbismuth in solution within the beta-Sn matrix provided an increased resistanceto the Ostwald ripening diffusion process that coarsens the Ag-Sn IMCparticles.  The combination of these two effects in the SAC+Bi alloyslead to greatly improved resistance to aging induced effects relative to thestandard SAC solder alloys.  Finally, we have compared the timedependent evolution of microstructure with the degradation in strength duringaging for both SAC and SAC+X alloys, and good correlations were observed.

 

 

Invited-05: Cooling of high-powermicroelectronic components using flow boiling

Prof Yogendra Joshi, Georgia Instituteof Technology

With the continuing trend towardsheterogeneous integration, volumetric power densities are likely toincrease.  Microfluidic two-phase cooling provides a potential solution toachieve high heat transfer capabilities, and high temperature uniformity in thepresence of hot spots.  This presentation will present an approach forcomputational simulations of flow boiling for chip cooling, illustrated withmultiple examples.  Also presented will be experimental validations of thecomputations.

 

 

Invited-06: Development of multi-chipintegration non-molded 2.5D IC Packaging Technology

Dr Chen Wei Chung, Curry, Technical Consultant, ASE Global

Recent requirements for 2.5D IC packagewith high bandwidth and high-performance applications is bringing molded andnon-molded 2.5D packaging technology innovations into another level. Ourproduction and development experience in non-molded 2.5D devices include 20 ×20 mm2 to 70 × 70 mm2 packages with 2 to 5chips. Non-molded package has benefits such as cost saving and variable thermalsolutions, however the warpage control and stress distribution always becomechallenges and constraints for larger module hardware. Package design, advancedmaterial selection and process design for stress and warpage control will beillustrated in this presentation. Practical process with reliability resultscombine with stress simulation data will be discussed as well.

 

 

Invited-07:  Evolution of Fault Isolation Techniques forProduct Failure Analysis

Dr Goh Szu Huat ,Deputy Director, GlobalFoundries Singapore

The mission of global faultlocalization is to narrow the physical inspection area to as small and accurateas possible. This is vital to increase the chance of failure analysis success.Against the backdrop of chip scaling, advanced packaging architectures as wellas the prevalence of more complex failure types, conscientious efforts toexamine and refine custom fault isolation techniques is crucial to achieve thismission. This talk describes the overall trends in both die and package-levelfault isolation techniques. The underlying challenges and motivations thatdrive these enhancements will also be discussed.

 

 

 

Invited-08: Micro-interconnects: SignalIntegrity in 5G Applications

Dr Murali Sarangapani, Senior PrincipalResearch Engineer, Heraeus Materials Singapore Pte Ltd

This presentation deals with twoaspects on micro-interconnects in semiconductor packaging. First, recentdevelopments in wire bonding, soldering, sintering primarily designed for lowelectrical resistivity are reported. Second, these wire-bonded, sintered andsoldered structures satisfy low loss in transmitting wide bandwidth signals in5G applications are discussed. 

In bonding wire technology, bare andpalladium coated copper wires have positioned themselves in high volumereplacing gold bonding wires successfully. Alloyed silver wires are used in LED.Gold coated silver wires are studied for memory applications using cascadebonding method. Low temperature bismuth-tin solders have been examined for thelast few decades and currently are popular in the usage to reduce warpage(zero) and electrical power consumption. The reflow temperature of thesesolders are aimed to be less than 190°C. Sintering with nanoparticles reducesprocess temperature by rapid necking. Using bi-modal electrically conductivepowder particles and composite materials, Heraeus-innovation team exploressintered interconnects to process with low reflow/sinter temperatures. Inaddition, the sintered interconnects possess low insertion losses with goodsignal and power integrity. The talk concludes with a challenge to researchersto develop new interconnect materials without limiting the boundaries betweenelectrical resistivity and high-volume production, while still aiming toinnovate micro-interconnects with unified performance that blends signalintegrity with low insertion loss and low electrical/thermal resistivity.

 

 

Invited-09: Development of NovelPolymer Materials for Advanced Packaging

Dr Takenori Fujiwara, Senior ResearchAssociate, Toray Industries

The advanced packaging market will growdramatically. Advanced packages will continue their important role ofaddressing high-end logic and memory in computing and telecom, with furtherpenetration in analog and RF in high-end consumer/mobile segments. All of thiswhile eyeing opportunities in the growing automotive and industrial segments.

 

To fulfil next-generation hardwareperformance requirements, advanced packaging must press for innovations inprocess, materials, and equipment. Indeed, advanced packaging has acceleratedthe need for breakthrough technologies in substrate manufacturing, packageassembly, and test engineering. As for materials, there is a desire to developnew dielectric materials, mold compounds, underfill (including Non-conductive film(NCF),solder interconnects.

Temporary Bonding De-Bonding materials(TBDBs) and thermal interface materials (TIMs) for fulfilling the stringentperformance and reliability requirements demanded by next-generation hardware.Also, the need for breakthroughs in package feature-scaling requires a sense ofurgency from key suppliers to the semiconductor packaging industry.

This report covers the trends andchallenges specific to advanced packaging materials technology, and includesdetailed technical roadmaps for various packaging materials based on ourmaterials. 

 

 

 

 

Invited-10: Virtual prototyping forelectronic packaging development, dream or reality? -Bridging thegap between Simulation and Reality in electronic packaging

Dr Jing-En Luan, R&D Manager, STElectronics

New product or module development isvery challenging nowadays. The development cycle time is shortening, andreliability requirement is higher and higher. CAE is widely used in packagedevelopment. Simulation become more and more important in new productdevelopment. Industry is pursuing virtual prototyping for new product.

However, the accuracy of the models andsimulation results is one of the biggest limitations that virtual productdevelopment engineers have today. in the product or package development team,there is always challenging and argument how to use simulation results.Engineers from different background have different opinions. The PM/ EPM mayhave difficulty to understand or believe the results.

In the presentation, the author willshare the product/package development flow. The key milestones duringdevelopment. And how modeling supports it for virtual prototype and keylimitation. The author will share examples on each key area to bridge the gapbetween simulation and experiment or reality.

Virtual prototyping is possible withimprovement in key area while designer/simulation engineer/material test /engineer work together. It make a higher level of integration not onlyengineering but also manpower.


 

Invited-11:  A comprehensiveReliability  Assessment on 2.5D and 3D Integration

Mr Premachandran CS, Senior Member ofTechnical Staff, Globalfoundries (USA)

Prem (Premachandran,CS) holds a Master’s degree in Engineering fromIndian Institute of Technology (IIT), Chennai, India and  is currentlyworking in GLOBALFOUNDRIES, Malta, NY. He has published more than 70publications in journals/conferences,holds more than 25 patents awarded/pendingand has co-authored an engineering book in MEMS Packaging. He has given invitedtalk and tutorials in EPTC, ECTC and IRPS conferences. He is a senior member ofIEEE and has session chaired in many conferences and has received a best paperaward in IITC 2014. 

System level  integration on logic and memory has been an importantsubject to packaging community for mobile and HPC( High performance computing)applications. Recent years, 3DIC integration technology has advanced fromsubstrate level package to wafer level system integration. Wafer levelintegration  leads the semiconductor  industry into a new era ofsystem scaling beyond Moore's Law. This talk will  give the requirementof   reliability  aspects on 3D  fine pitch  wafer towafer bonding  and 2.5D interposer on 65nm  technology which is setto go  on volume production.

 

 

Invited-12: System Packaging Solutionsfor High Performance Computing in the Era of 5G/IoT

Mr. Shunichi Kikuchi, Corporate VicePresident, Fujitsu Advanced Technologies Limited

High Performance Computers have beenextending the performance in order to computationally solve intensive tasks invarious fields, combining a variety of packaging technologies. The transitionin their performance can be seen in the past ToP500 lists. The list whichdiscloses High Performance LINPACK (HPL) benchmark scores from No.1 to No.500is updated twice a year. Through the data analyses of the past ToP500 lists inthe past 26 years, several findings and current trends from the viewpoint ofsystem packaging can be shared with audience. With processor packaging trends,high speed interconnects and other promising technologies, a few systempackaging solutions will be introduced for future high-performance computing.Moreover, I will also explain about newly prepared measurement methods in orderto implement the above system packaging. Finally, I will present a direction ofsystem packaging for the era and beyond, including challenges facing thesustainable development goals.

 

 

Invited-13: Plasma process optimization for Cu bonding integration usingthe design of experiment technique

Prof Sarah Kim ,Seoul NationalUniversity of Science and Technology

The vertically stacked devices called3D integrated circuit packaging have been focused to realize an extrememiniaturization, a cost reduction and more functionality. Among three coreprocesses in 3D IC packaging, a wafer bonding process is still an immatureprocess for D2W mass production compared to TSV and wafer thinning process.Especially with the demand of fine-pitch interconnection, Cu bonding is ofgreat interest in 3D IC heterogeneous packaging. In this study, a lowtemperature Cu bonding is evaluated with the formation of copper nitridepassivation layer, which its optimization was carried out by the design ofexperiment technique. The bonding quality by SAT measurement, 4PB measurement,and SEM measurement and the lifetime reliability of nitride passivation layerwill be discussed.

 

 

 

Invited-14: Novel MEMS based LateralContact Probing Method for Fine Pitch Micro-bumps for High Bandwidth Memory(HBM) Testing

Dr Daniel Rhee Min Woo, ProgramManager, Samsung Korea

The conventional pre-bond testingmethod operates probes vertically on micro-bumps, and the contacted tip end ofthe micro-bumps inevitably gets damaged. This is detrimental to the ICassembly, which is the post-testing stage, because it causes a defectivejunction problem. To overcome this problem, we proposed lateral contact probingof fine pitch micro-bumps because it does not damage the tip end of themicro-bumps at all. We successfully demonstrated the testing, for the firsttime, with monolithically fabricated fine pitch probes. In addition, whereasconventional probes require a very complicated fabrication process for highflexibility to reduce the damage to the micro-bumps, another feature in thiswork is that the probes do not need high flexibility or complex fabrication.Thanks to the simple structure of the probes for the lateral contact, thefabrication is designed with only one thick negative PR mold and nickelelectroplating to construct it all. The fabricated probes were laterally drivenas much as 7μm without plastic deformation, which is acceptable considering theerror in the plane direction of chips. In addition, the tested probes wererepeatedly driven 5μm for 100,000 cycles and their CCC was at least larger than180 mA. With these probes, we successfully demonstrated contact withoutdegradation on the tip end of the micro-bumps and the measured contact resistancewas 1.13, the highest. All the side-walls of the micro-bumps showed low damageregardless of the material. Moreover, about 10,000 probes were uniformlyfabricated in a batch process. By employing the proposed concepts with all theresults we had, we expect this lateral contact probing method is a prospectivesolution for pre-bond testing of modern advanced fine-pitched micro-bumps.

 

 

Invited-15: Importance of WarpageEngineering in the era of Heterogeneous Integration

Prof SB Park, State University of NewYork at Binghamton

As Moore’s law is being challenged byincreased cost and physical limitations, many forms of SIP (System in Package)including Heterogeneously Integrated Packages are rising as alternativesolutions and practical breakthrough. Regarding SIP, naturally, the deformationof a package and its assembly become more complicated. The need for throughunderstanding its behavior is ever increasing for higher yield in manufacturingas well as better reliability for operation. In this presentation, a methodthat makes modeling more reliable and dependable is introduced with some casestudies. Starting from the detailed material characterization, adjustment ofthe measured properties, and confirmation of the effectiveness by the measuredwarpage are included. In addition, 3D-DIC, a new method of quantifying thedeformation of a package during reflow, is introduced.

 

 

Invited-16: Material Advancement forHeterogenous Integration

Dr Dongshun Bai, Director, Brewer Science

Heterogenous integration (HI) hasincreasingly attracted attention in the semiconductor industry. In HI,separately manufactured components with different materials, sizes,thicknesses, functionalities, and process technologies can be integrated into ahigher-level system to provide enhanced functionality and improved operatingcharacteristics. HI needs new materials in semiconductor, conductor,dielectric, molding, and die-attach applications.  Through rational structuraldesign, we can control many physical and chemical properties of the materialsto achieve the desired performance. In this talk, new material development atBrewer Science for HI will be introduced. The approach for innovative materialdesign and specific examples including new temporary bonding and debondingmaterials, novel permanent materials, and materials for adhesion promotion andcopper protection applications will be presented.

 

 

Invited-17:   InnovativePackage Solution for 5G Era

Dr. Yu-Po, Wang, Director, SPILCorporate R&D Centre

In 1997, hestarted career at Gintic Institute of Manufacturing Technology in Singapore. Hehas jointed SPIL since 1998 and led the R&D advanced packaging design teamfor leadframe, substrate and wafer form packages development.

Dr. Wang hasstrong knowledge and experience in packaging characterization includingthermal/ electrical simulation, advanced material(co-development), design andadvanced packaging development. He has 83 patents in US.

Dr. Wang hasstrong knowledge and experience in packaging characterization includingthermal/ electrical simulation, advanced material(co-development), design andadvanced packaging development. He has 83 patents in US.

 

 

Invited-18: Package Design Challengesfrom 5G for Next Generation Memory Technologies

Dr Gokul Kumar, Senior Manager, PackageDesign and Development, Micron

Dr. Gokul Kumar has around ten year’scumulative experience in electronic packaging. He has a multi-disciplinarybackground encompassing package design, physical design/layout, signal/powerintegrity, substrate fabrication, technology validation and productdevelopment. He currently serves as a Principal Engineer with Western Digital, USA.In this capacity, he has championed several key contributions to Flash Memoryand Memory-centric ASIC products over the last 5 years.He has co-authored over15 journal and conference publications, which have been cited over 450 times.He also has 5 United States Patents in the area of memory-logic integration. Inaddition, Dr. Kumar is a peer reviewer for a number of internationallyreputable conferences and journals. He has also served on several technicalpanel committees, in addition to being the technical invited speaker at theIEEE Electronics Packaging Technology Conference for the last couple of years.


Co-integration oflogic and memory stacks (both DRAM and NAND) into extremely miniaturizedpackages has been at the forefront of mobile and consumer semiconductorinnovation. With the recent advent of 5G and other data-centric designapplications, this has created several opportunities for exponential growth.However, the challenges from 3-D NAND and DRAM co-integration have also posedseveral design bottlenecks in achieving low-cost packages that meet electrical,thermal and mechanical requirements. This talk will serve to highlight boththese opportunities as well as the package design challenges to be overcome toachieve required performance.

 

Invited-19: Effects of trace element onelectromigration of flip chip interconnect between Cu Pillar and Sn-Bi alloysystem

Mr Murayama Kei, Research andDevelopment Consultant, Shinko Electric Japan

From environmental issues, economicsand technical points of view, the demands for low temperature soldering isincreasing year by year. Sn - Bi solders are powerful candidate materials torealize its demands. We investigated effects of surface finish and traceelement on electro-migration of flip chip interconnection between Cu-pillar andCu or Cu/Ni/Au pad using Sn-Bi solder alloy system by Electron backscattereddiffraction (EBSD) and Electron probe micro analyzer (EPMA). We introduce thatAu, Pd and Ni trace element influence on electro-migration resistance. Au, Pdatoms play a role of accelerating diffusion Ni into Cu6Sn5. When Au and Pdatoms were small, Inter-metallic compounds growth at Cu pillar side is limited.On the other hand, in case of existing small amount of Ni atoms in solder, theyform dense scallop type (Cu,Ni)6Sn5 layer at substrate pad and acted as aneffective barrier against diffusion from Cu or Ni pad.

 

 

  

Invited-20:  What is new for thefast learning of IC Reliability - Advanced Defect Learning, Package StructuralTesting, & Reliability modelling by HPC

Mr Xue Ming, Lead Principal FailureAnalysis, Infineon

IC package reliability fails areoccurred typically with time, loading stress, and environmental stress, whichis often escaped from manufacturing test. Package structural fault is a commonearly deviations cause reliability failures, for example, wire near short,lifted ball bond, die crack. To learn and implement control in manufacturingprocess for package structural fault is slow as limited detection and take timewith conventional approach. A number of new approach are in our horizon,Package structural fault test, Advanced defect learning, and Reliabilitymodelling with High performance computing. This talk will present to you thestate of the art and leading development in this topic.



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