EPTC

Invited Speakers

1. Flexible and Stretchable Meta-surface Skins Integrating Energy-Efficient Adaptive Electronics, Dr. Sidina Wane, President, Founder and CEO of eV-Technologies

2. Glass Core Substrate Market and Opportunity, Dr. Tan Yik-Yee, Senior Technology & Market Analyst, Semiconductor Packaging at Yole Group

3. Die to Wafer Hybrid and Fusion Bonding to Enable Advanced Packaging Applications,Dr. James Stephen Papanu, Senior Director, 3DI Technology, Tokyo Electron Limited

Die-to-Wafer Hybrid and Fusion Bonding to Enable Advanced Packaging Applications

James S. Papanu, Tokyo Electron Corporate Innovation Dept. and TEL Technology Center, America

Die-to-wafer (D2W) hybrid and fusion bonding are critical enablers for 3DI applications. An integrated approach comprising test vehicle design and cluster tool development for high-volume manufacturing has been implemented. High-yield bonding requires well-controlled surface preparation, defect/contamination-free interfaces, and precise die placement. Unique to our cluster tool approach is a TEL Clean Carrier (TCC) that mitigates organic contamination associated with tape frame carriers, and in turn can enhance customer bonding yield and subsequent package yield. The TCC approach also allows for leveraging of existing platform, plasma chamber, and wet processing chamber designs and technology without scaling these platforms and chambers to accommodate tape frames. Furthermore, this cluster tool incorporates plasma and wet processing surface preparation expertise from production-proven wafer-to-wafer bonding tools.

The application space for logic and memory D2W bonding consists of a broad range of die sizes, thicknesses, and aspect ratios. We have demonstrated baseline process and TCC functional capability for large die sizes of up to 30x30 mm2 and ultrathin 30 um die bonding/stacking for HBM applications using blanket dielectrics, and we are also developing capability for bonding of high aspect ratio die. Patterned test vehicles (TV) with 4.5 um and 3.0 um bond pad pitches have been designed and fabricated at the TEL Technology Center, America facility. The upper (component die) and bottom (target) wafers both have three levels of metallization, with die on the bottom wafer being larger to accommodate electrical test pads on the periphery. The TV fabrication can be short looped for initial bonding interface and alignment quality checks via CSAM and SEM/FIB cross-sections, or full 3-level metallization for electrical testing. These patterned TV’s currently have die areas and aspect ratios of approximately 50-100 mm2 and 1:1, respectively. Additional test TV designs, such as for significantly larger die sizes, are being planned. As customer hybrid bonding placement accuracy roadmaps push to 100 nm followed by 50 nm, these new TV designs also incorporate features to evaluate both sensitivity to fiducial design and advanced metrology concepts.

In this paper an overview of the TEL test vehicles, TCC, surface preparation chambers, tool platform, and die bonding module will be presented along with representative process data and a perspective on meeting future placement accuracy roadmaps.

Biography

James Stephen Papanu is a distinguished engineering and technology leader with over 35 years of experience in the semiconductor industry, specializing in semiconductor packaging, wafer fabrication, and PV/glass coating. As Senior Director at Tokyo Electron Limited, Mr. Papanu oversees the development of advanced semiconductor technologies, particularly in die-to-wafer and wafer-to-wafer hybrid bonding, plasma etching, and advanced packaging. Prior to this, he served as Technology Director for Advanced Packaging Applications at Applied Materials (AMAT), where he led critical development projects in die singulation and cluster tool integration. His leadership at AMAT resulted in the successful qualification of new toolsets for high-volume production.

Throughout his career, Mr. Papanu has been awarded 63 patents, reflecting his significant contributions to plasma processing, surface conditioning, and innovative semiconductor manufacturing techniques. His expertise in the development and commercialization of cutting-edge technologies has made him a key figure in advancing both front-end and back-end semiconductor processes. Mr. Papanu’s work has spanned the entire product lifecycle, from initial concept and feasibility to customer engagement and product release.

With a Ph.D. in Chemical Engineering from UC Berkeley, Mr. Papanu has also authored numerous technical publications and is frequently invited to speak at international conferences. His ongoing leadership in the field continues to shape the future of semiconductor technology, making him a valuable contributor to the industry's advancements.

Glass Core Substrate Market and Opportunity

Glass core substrate gained a lot of attention since Intel announced the planning to adopt this material in September 2023. Intel said, “Glass substrates help overcome limitations of organic materials by enabling an order of magnitude improvement in design rules needed for future data centers and Artificial Intelligence (AI) products.” It is clear, hype in demands for AI is the mega trends of this century. It requires a system with higher transmission speeds and bandwidths. The organic substrate is facing the challenge to meet future system requirement. Introducing glass core substrate material as alternative to overcome the bottleneck of organic substrate is promising. This presentation will share the glass core substrate opportunity in different market. In depth discussion on the challenges and opportunities. Last, how the supply chain reaction and readiness.

Biography

Dr. Tan Yik-Yee is a Senior Technology & Market Analyst, Semiconductor Packaging at Yole Group, within the Semiconductor Manufacturing & Global Supply Chain Business Line. Yik Yee Tan holds a Ph.D. in Engineering from Multimedia University (MMU, Malaysia). She has more than 25 years of experience in semiconductor packaging. Based on her technical expertise and market knowledge, she develops technology & market reports and is engaged in dedicated custom projects. Prior to Yole, Yik Yee Tan worked as a failure analyst and interconnect principal at Infineon Technologies (Malaysia) and later as an open innovation senior manager at Onsemi (Malaysia). While at Onsemi, Yik Yee was deeply involved in numerous innovative advanced packaging projects. She published more than 30 papers and hold 3 patents.

Abstract

‘Smart Integrated Electromagnetic Skins’, that are conformal to the shape of the object they are mounted on, are introduced in the scope of the European Project FITNESS (Flexible IntelligenT NEar-field Sensing Skins) [1-2]. The underlying technological solution offers a replacement for the concept of “elements” in arrays over a textured surface (“Metasurface”) that is fed by a limited number of source points (or “ports”), through which the electronics can sense the near-field and far-field electromagnetic environment and adapt to it. The proposed approach of co-design and co-integration of metasurface (MTS) with 3D heterogeneous front-end-modules (FEM) accounts for thermal-dissipation management and accommodates curved and flexible electronic substrates. The resulting requirements call for new functional materials engineering with challenges in relation with processes and circuits EM-Thermal-Mechanical co-design and co-assembly. New designs and realizations are manufactured and experimentally evaluated. This work demonstrates for the first time, co-integration of dual-channel MTS antenna and transceiver FEMs using 3D heterogeneous packaging with the benefits of Multi-Feed (MF) Chip-in-Connector (CiC) technologies. At the system-level, the measured performance of MTS with adaptive FEMs is reported for multi-user MIMO applications.

This potentially paves the way to countless applications, particularly in measurement and sensing systems, such as robots or other autonomous mobile system that may use conformal MTS as a “smart skin”. The sensing of nearby objects (size, position and distance) is enabled by the correlation of signals transmitted and received by all pairs of ports connected to the surface. The use of time-modulated correlation functions can foster new FEM architectures using emerging energy-aware technologies with functionalities including direction of arrival (DOA) estimation and secure communications. At baseband frequencies, FPGA and ASIC/DSP-based convolutional accelerators using correlation-based metrics [3-6] accounting for non-linearities are assessed toward joint sensing & communication. An envisioned holistic MTS-Electronics EM-Thermal-Mechanical co-design approach will enable new noise-aware formulations based on Fluctuation-Dissipation-Theorem (FDT) [7] for the design of functionalized flexible & stretchable MTS-based coatings that can adapt themselves to the surrounding environment.

Biography

Sidina Wane is President, Founder and CEO of eV-Technologies – a high-technology company providing leading edge energy-aware tools, instrumentations and chip-package-PCB-antenna co-design solutions for RF, millimeter-waves and optical applications. Sidina Wane holds a Dr.-Ing.-HDR degree in electronic circuits and systems working on chip-package-PCB co-design, co-simulation, and experimental co-verification. His main interest is in the field of power integrity, signal integrity, EMC (electromagnetic compatibility) and EMI (electromagnetic interference) in integrated circuits/systems for RF (radio frequency), mm-wave, and Optical applications. He holds several European and US patents and numerous academic and industrial awards with more than 20 years experience in the semiconductors industry.