Invited talk #1

Title: D2W Hybrid & Fusion Bonding to Enable Advanced Packaging

Speaker: James Papanu, Tokyo Electron Limited

Bio:

James Stephen Papanu is a distinguished engineering and technology leader with over 35 years of experience in the semiconductor industry, specializing in semiconductor packaging, wafer fabrication, and PV/glass coating. As Senior Director at Tokyo Electron Limited, Mr. Papanu oversees the development of advanced semiconductor technologies, particularly in die-to-wafer and wafer-to-wafer hybrid bonding, plasma etching, and advanced packaging. Prior to this, he served as Technology Director for Advanced Packaging Applications at Applied Materials (AMAT), where he led critical development projects in die singulation and cluster tool integration. His leadership at AMAT resulted in the successful qualification of new toolsets for high-volume production.

Throughout his career, Mr. Papanu has been awarded 63 patents, reflecting his significant contributions to plasma processing, surface conditioning, and innovative semiconductor manufacturing techniques. His expertise in the development and commercialization of cutting-edge technologies has made him a key figure in advancing both front-end and back-end semiconductor processes. Mr. Papanu’s work has spanned the entire product lifecycle, from initial concept and feasibility to customer engagement and product release.

With a Ph.D. in Chemical Engineering from UC Berkeley, Mr. Papanu has also authored numerous technical publications and is frequently invited to speak at international conferences. His ongoing leadership in the field continues to shape the future of semiconductor technology, making him a valuable contributor to the industry's advancements.

Abstract:

Die-to-wafer (D2W) hybrid and fusion bonding are critical enablers for 3DI applications. An integrated approach comprising test vehicle design and cluster tool development for high-volume manufacturing has been implemented. High-yield bonding requires well-controlled surface preparation, defect/contamination-free interfaces, and precise die placement. Unique to our cluster tool approach is a TEL Clean Carrier (TCC) that mitigates organic contamination associated with tape frame carriers, and in turn can enhance customer bonding yield and subsequent package yield. The TCC approach also allows for leveraging of existing platform, plasma chamber, and wet processing chamber designs and technology without scaling these platforms and chambers to accommodate tape frames. Furthermore, this cluster tool incorporates plasma and wet processing surface preparation expertise from production-proven wafer-to-wafer bonding tools.

The application space for logic and memory D2W bonding consists of a broad range of die sizes, thicknesses, and aspect ratios. We have demonstrated baseline process and TCC functional capability for large die sizes of up to 30x30 mm2 and ultrathin 30 um die bonding/stacking for HBM applications using blanket dielectrics, and we are also developing capability for bonding of high aspect ratio die. Patterned test vehicles (TV) with 4.5 um and 3.0 um bond pad pitches have been designed and fabricated at the TEL Technology Center, America facility. The upper (component die) and bottom (target) wafers both have three levels of metallization, with die on the bottom wafer being larger to accommodate electrical test pads on the periphery. The TV fabrication can be short looped for initial bonding interface and alignment quality checks via CSAM and SEM/FIB cross-sections, or full 3-level metallization for electrical testing. These patterned TV’s currently have die areas and aspect ratios of approximately 50-100 mm2 and 1:1, respectively. Additional test TV designs, such as for significantly larger die sizes, are being planned. As customer hybrid bonding placement accuracy roadmaps push to 100 nm followed by 50 nm, these new TV designs also incorporate features to evaluate both sensitivity to fiducial design and advanced metrology concepts.

In this paper an overview of the TEL test vehicles, TCC, surface preparation chambers, tool platform, and die bonding module will be presented along with representative process data and a perspective on meeting future placement accuracy roadmaps.

Invited talk #2

Title: Glass Core Substrate Market and Opportunity

Speaker: Tan Yik-Yee, Yole Group

Bio:

Dr. Tan Yik-Yee is a Senior Technology & Market Analyst, Semiconductor Packaging at Yole Group, within the Semiconductor Manufacturing & Global Supply Chain Business Line. Yik Yee Tan holds a Ph.D. in Engineering from Multimedia University (MMU, Malaysia). She has more than 25 years of experience in semiconductor packaging. Based on her technical expertise and market knowledge, she develops technology & market reports and is engaged in dedicated custom projects. Prior to Yole, Yik Yee Tan worked as a failure analyst and interconnect principal at Infineon Technologies (Malaysia) and later as an open innovation senior manager at Onsemi (Malaysia). While at Onsemi, Yik Yee was deeply involved in numerous innovative advanced packaging projects.  She published more than 30 papers and hold 3 patents.

Abstract:

Glass core substrate gained a lot of attention since Intel announced the planning to adopt this material in September 2023. Intel said, “Glass substrates help overcome limitations of organic materials by enabling an order of magnitude improvement in design rules needed for future data centers and Artificial Intelligence (AI) products.”  It is clear, hype in demands for AI is the mega trends of this century. It requires a system with higher transmission speeds and bandwidths. The organic substrate is facing the challenge to meet future system requirement. Introducing glass core substrate material as alternative to overcome the bottleneck of organic substrate is promising. This presentation will share the glass core substrate opportunity in different market. In depth discussion on the challenges and opportunities. Last, how the supply chain reaction and readiness.  

Invited talk #3

Title: Pulsating Heat Pipes for Electronics Cooling

Speaker: Winston Zhang, Novark Technologies

Bio:

L. Winston Zhang is the founder and CEO of Novark Technologies based in Shenzhen, China since 2004, and also an adjunct lecturer in the Department of Mechanical Science and Engineering at University of Illinois at Urbana-Champaign since 2022. He has three decades’ experience in the area of heat transfer and electronics cooling. He received his Ph.D. in mechanical engineering from the University of Illinois at Urbana-Champaign in 1996. He is a licensed professional engineer (P.E.) in the State of Wisconsin, USA and a Fellow of the American Society of Mechanical Engineers (ASME), Asia Liaison for the IEEE Annual Semiconductor Thermal Measurement and Management Symposium (SEMI-THERM), Track Co-Chair for the ASME International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems (InterPACK) and a board member of the Taiwan Thermal Management Association (TTMA).

Abstract:

Pulsating Heat Pipes are passive thermal transport devices characterized by a serpentine micro-channel loop that traverses back and forth from its evaporator and condenser zones. Within this micro-channel, liquid slugs and thin liquid films trapped between the wall and elongated bubbles undergo evaporation in the heated evaporator, with the resulting volumetric leading to self-instigated perpetual oscillations within the device. Pulsating heat pipes are beginning to be introduced into industrial cooling applications, such as power electronics and data-centers. In this talk, several case studies ranging from telecommunication base station cooling to power electronics cooling are presented.

 Invited talk #4

Title: Fluxless TCB for Chiplet Integration

Speaker: Chan Pin Chong, Kulicke & Soffa

Bio:

Chan Pin was appointed as Executive Vice President & General Manager, K&S' Products and

Solutions in December, 2019.

He joined K&S in 2014 as Vice President of Wedge Bonders business unit and has successfully

turnaround the business and led the team to higher growth by diversifying the business into the battery bonding market.

Chan Pin is a technology industry veteran with more than 24 years of engineering and

operations experience in the semiconductor and electronics industry. He started his career first as a Process and Test Engineer at Motorola Pagers and Cellular group and pioneered multiple factories in Asia before advancing to the role of Manufacturing Manager at Flextronics. In 1999, Chan Pin joined KLA-Tencor and held a number of diverse positions, including Senior Technical Director of Engineering and General Manager of Strategic Business Unit in Greater China. Chan Pin then pioneered the efforts of starting the MEMS factory in Singapore when he became the Vice President of Sales and General Manager at Form Factor. Most recently, he was the Global President & CEO at Everett Charles Technologies, managing and leading in test and probe technologies.

Chan Pin received his bachelor's degree in Electrical Engineering and Computer Science from

the State University of New York at Buffalo and a master's degree in Business Administration

from the University of Leicester, United Kingdom.

Abstract:

 As demands for high-performance computing for servers, artificial intelligence, and cloud applications continue to rise, the industry is pushed to have larger dies and denser I/O interconnects. As a result of these industry drivers, an aggressive approach to enable higher functional density and higher bandwidth packages is required. To overcome packaging interconnection challenges of below 35um pitch, a new revolutionary process with in-situ copper oxide and tin oxide reduction, with solutions reaching huge dies and fine-pitch chipsets. It also support in-situ Formic Acid (FA) vapor application for copper and solder oxide reduction. This Formic Acid fluxless TCB process eliminates the need for flux, reducing complexity and improving reliability. It allows for larger dies, higher-density interconnects, and fine-pitch chipsets, expanding application possibilities in high-volume manufacturing.

 Invited talk #5

Title: RDL-First Interposer Technology for Next Generation Advanced Packaging

Speaker: Chai Tai Chong, IME

Bio:

Mr. Chai Tai Chong is a Senior Principal Research Engineer at the Institute of Microelectronics (IME), A*STAR, with an impressive 30-year career in IC packaging research and development. His expertise spans a wide range of advanced packaging technologies, including Chip Scale Packaging (CSP), Fan-Out Wafer Level Packaging (FOWLP), 2.5D interposer packaging, and 3D System-in-Package (3D-SiP).

Throughout his career, Mr. Chai has led numerous industry consortia projects at IME, collaborating with global semiconductor companies to drive innovation and adoption of cutting-edge packaging solutions. He has been the Principal Investigator (PI) for several IME-led initiatives, demonstrating his deep technical knowledge and leadership in the field.

Currently, Mr. Chai is spearheading the HPC Photonic Chiplet Consortium, focusing on the integration of high-performance computing (HPC) and photonic chiplet technologies. His work aims to advance the capabilities of the next-generation packaging solutions, addressing the increasing demands of high-performance computing and artificial intelligence applications.

Abstract:

System-in-Package (SiP) solutions using chiplets are gaining significant interest as a way to overcome the limitations of traditional System-on-Chip (SoC) and board-level integration. These solutions enable reduced form factors, improved performance, and cost efficiencies. However, the increasing demands of generative AI require higher power and memory capabilities beyond what current 2.5D SiP architectures can provide. This presentation introduces a test vehicle that integrates high-performance compute, memory, and photonic chiplets on a large RDL-first interposer. It facilitates process integration, material evaluation, and reliability testing for high-density interconnections, including UCIe and HBM bridge interfaces. I will be discussing RDL-first technology as a promising platform for heterogeneous integration in next-generation advanced packaging. System-in-Package (SiP) solutions using chiplets are gaining significant interest as a way to overcome the limitations of traditional System-on-Chip (SoC) and board-level integration. These solutions enable reduced form factors, improved performance, and cost efficiencies. However, the increasing demands of generative AI require higher power and memory capabilities beyond what current 2.5D SiP architectures can provide. This presentation introduces a test vehicle that integrates high-performance compute, memory, and photonic chiplets on a large RDL-first interposer. It facilitates process integration, material evaluation, and reliability testing for high-density interconnections, including UCIe and HBM bridge interfaces. I will be discussing RDL-first technology as a promising platform for heterogeneous integration in next-generation advanced packaging.

 Invited talk #6

Title: Towards AI-Assisted Design of Thermal Management Strategies

Speaker: Hardik Kabaria, Vinci4D

Bio:

Hardik Kabaria is the CEO and co-founder of Vinci4D, where his team is building the co-pilot for hardware engineers and designers. Their goal is to accelerate the design process by 10X through proprietary foundation models for precision 3D geometries and physics. A key application of these models is enabling designers to perform physics simulations 100 times faster, seamlessly integrated into their existing workflows. Their first application is heat conduction simulation of really complex geometries seen in advanced packaging and increasing the via density.

Hardik holds a Ph.D. in Computational Geometry and Mechanics from Stanford University. After completing his doctoral work, he joined Carbon3D, a 3D printing startup, where he served as VP of Software. In this role, he led the development of software systems that bridged design and manufacturing.

Abstract:

We introduce Vinci-Thermal©, an AI-assisted tool to quickly compute the temperature distribution of complex electronic components. Trained with thousands of cases, we show that it can compute temperature distributions and effective conductivities over complex redistribution layer-inspired geometries in a few seconds. Additionally, Vinci-Thermal© incorporates a hierarchy of progressively accurate models to always return an answer with the desired accuracy. When used in conjunction with a tiling strategy, Vinci-Thermal© can compute temperature distributions over large components.