Professional Development Courses
There are 5 Professional Development Courses (PDC) to be conducted by leading experts in the respective fields during the conference. Each PDC has been approved by IEEE to receive 0.3 Continuing Education Units (CEUs) or 3 Professional Development Hours (PDHs). CEUs and PDHs are recognized internationally by employers for continuing professional development as a formal measure of participation and attendance in “non-credit” self-study courses, tutorials, symposia, and workshops. Each course will be conducted virtually (unless specified) with a duration of about 2 to 2.5 hours. Only registered PDC attendees will receive the PDC softcopy handouts, and 1-1 Q&A via emails with the lecturers.
PDC 1: Antenna-in-Package (AiP) Technology for Millimeter-Wave Applications
Instructor: Y. P. Zhang, Nanyang Technological University, Singapore
Course Objective: Antenna-in-package (AiP) technology integrates an antenna or antennas with a radio or radar transceiver die (or dies) into a standard surface mount package. AiP technology well balances performance, size, and cost. Hence, it has been widely adopted by chip makers for highly integrated radios and radars. It is the antenna and packaging technology for the ﬁfth generation (5G) cellular networks and beyond operating in the millimetre-wave (mmWave) bands. This PDC will provide an overview of the development of AiP technology. It will consider antennas, packages, and interconnects for AiP technology. It will show that the antenna choice is usually based on those popular antennas that can be easily designed for the application and that the materials and processes choices involve trade-offs among constraints, such as electrical performance, thermal-mechanical reliability, compactness, manufacturability, and cost. This PDC will also show a probe-based setup to measure mmWave AiP impedance and radiation characteristics. It goes on to highlight wire-bond AiP (WB-AiP), flip-chip AiP (FC-AiP), and fan-out AiP (FO-AiP) with examples.
Biography: Prof. Yueping ZHANG is a full Professor with the School of Electrical and Electronic Engineering at Nanyang Technological University, Singapore, a Distinguished Lecturer of the IEEE Antennas and Propagation Society (IEEE AP-S), a Member of the IEEE AP-S Paper Award Committee, and a Fellow of IEEE. Prof Zhang has published numerous papers, including two invited and one regular papers in the Proceedings of the IEEE and one invited paper in the IEEE Transactions on Antennas and Propagation. He is the Chinese radio scientist who has published a historical article in an English learned journal such as the IEEE Antennas and Propagation Magazine. He received the 2012 IEEE AP-S Sergei A. Schelkunoff Prize Paper Award.
Prof Zhang has been delivered plenary, keynote, and invited speeches at the flagship conferences organized by IEEE, CIE, EurAAP, and IEICE. He received the Best Paper Award from the 2nd IEEE/IET International Symposium on Communication Systems, Networks and Digital Signal Processing, July 18–20, 2000, Bournemouth, U.K., the Best Paper Prize from the 3rd IEEE International Workshop on Antenna Technology, March 21–23, 2007, Cambridge, U.K., and the Best Paper Award from the 10th IEEE Global Symposium on Millimetre-Waves, May 24–26, 2017, Hong Kong, China.
PDC 2: Packaging and Heterogeneous Integration for Automotive Electronics, and Advanced Characterization of EMCs
Instructor: Przemyslaw Gromala, Robert Bosch GmbH, Germany
Course Objective: Epoxy-based molding compounds (EMCs) are widely used in the semiconductor industry as one of the most important encapsulating materials. For the advanced packaging technologies and heterogeneous integrations, EMCs play a more significant role than for the conventional plastically encapsulated packages because of thin profiles and complex process conditions required for the advanced packaging technologies. In the automotive industry where demand for more advanced packaging technologies increases rapidly for autonomous and connected cars, EMCs are often used to protect not only individual IC components but also entire electronic control units (ECUs), or power modules.
The stress caused by the mismatch of the coefficient of thermal expansion (CTE) between EMCs and adjacent materials is one of the major causes of reliability problems (e.g., excessive warpage, delamination, BRL, etc.). During assembly or even operating conditions, EMCs are subjected to temperatures beyond the glass transition temperature. Around the glass transition temperature, EMCs exhibit significant volumetric and isochoric viscosity, which leads to nonlinear viscoelastic behavior. In contrast, at low temperatures, EMCs show linear viscoelastic behavior. This complex material characteristic in the full temperature range of interest renders the design of electronic devices a nontrivial task. The mechanical behavior of EMCs must be understood clearly to offer predictive simulation strategies, which has become an integral part of product development process.This training will address details of such strategies, summarizes the required material characterization procedure, and closes with some representative examples
Biography: Dr.Przemyslaw Gromala is a simulation senior expert at Robert Bosch GmbH, Automotive Electronics in Reutlingen. Currently leading an international simulation team and FEM verification lab with the focus on implementation of simulation driven design for electronic control modules and multi - chip power packaging for hybrid drives. His research activities focus on virtual pre-qualification techniques for development of the electronic control modules and multi-chip power packaging. His technical expertise includes material characterization and modeling, multi-domain and multi-scale simulation incl. fracture mechanics, verification techniques, prognostics and health management for safety related electronic smart systems.
Prior joining Bosch Mr. Gromala worked at Delphi development center in Krakow, as well as at Infineon research and development center in Dresden. He is an active committee member of the IEEE conferences: ECTC, EuroSimE, ICEPT; ASME: InterPACK. Active committee member of EPoSS – defining R&D and innovation needs as well as policy requirements related to Smart Systems Integration and integrated Micro- and Nano systems. He holds a PhD in mechanical engineering from Cracow University of Technology in Poland.
PDC 3: Fan-out, Chiplets and Hybrid Bonding
Instructor: John H Lau, Unimicron Technology Corporation
Course Objective: Fan-out packaging has been getting lots of tractions since TSMC used their integrated fan-out (InFO) to package the application processor for the iPhone in 2016. The fundamental, recent advances and trends of fan-out packaging will be presented. Chiplets have been very popular since DARPA’s CHIPS (common heterogeneous integration and IP reuse strategies) program initiated in 2017. Microprocessors such as AMD’s EPYZ and Intel’s Lakefield have been in high volume manufacturing with chiplet designs and heterogeneous integration packaging. The state-of-the-art and outlook of chiplets will be provided. Hybrid bonding has been getting lots of attention since Sony extended their license of “Zibond” to include Ziptronic’s DBI (direct bond interconnect) in 2015 and used for manufacturing the CMOS image sensors and other image-based devices in 2016. The fundamental, recent advances and trends of hybrid bonding will be presented.
Biography: Dr.John H Lau with more than 40 years of R&D and manufacturing experience in semiconductor packaging, John has published more than 500 peer-reviewed papers, 30 issued and pending US patents, and 22 textbooks on, e.g., Advanced MEMS Packaging (McGraw-Hill, 2010), Reliability of 2D and 3D IC Interconnects (McGraw-Hill, 2011), TSV for 3D Integration, (McGraw-Hill, 2013), 3D IC Integration and Packaging (McGraw-Hill, 2016), Fan-out Wafer-Level Packaging (Springer, 2018), Heterogeneous Integrations (Springer, 2019), Assembly and Reliability of Lead-Free Solder Joints (Springer, 2020), and Semiconductor Advanced Packaging (Springer, 2021). John is an elected ASME Fellow, IEEE Fellow, and IMAPS Fellow.
PDC 4: Flip Chip Interconnect Technologies
Instructor: Eric Perfecto, IBM Corporation and Shengmin Wen, Synaptics Inc.
Course Objective: This course will cover the fundamentals of all aspects of flip chip assembly technology, Thermal compression bonding, substrate selection, solder joint and non-solder assembly processes, underfill, and reliability evaluation. The course is divided into two major sections.
The first section focuses on the key steps of flip chip assembly processes and their respective equipment that are involved. Plenty of examples are presented to show the versatile flip-chip applications to single die, monolithic multi-die, multi-level multi-die flip chip integration, as well as multi-form interconnection such as wire bond / flip chip mixed integration – the SiP integration. At the same time, major flip chip assembly packages are discussed, such as the BGA packages, CSP packages, wafer-level fan-in and fan-out packages, chip-on-chip packages, chip-on-wafer packages, and 2.5D/3D flip chip packages, together with actual industrial leading application cases. In-depth discussions include chip package interaction (CPI), package warpage control, yield detractors for flip-chip assembly, substrate technologies, failure modes and root cause analysis, reliability tests, and the important roles of electrical and mechanical simulation, Si die floor plan optimization and its consequence on packaging, among others. Students will understand the versatility of flip chip technologies and learn a range of criteria that they can apply to their daily work needs. This section also provides the trend in the flip chip assembly technologies.
The second section dives into the depth of the fundamental aspect of flip chip technology. It will detail the various interconnect technologies that are used in today’s flip chip assembly, i.e., lead-free solder bumping, highly customized Cu-Pillar bumping, intermetallic and Cu-to-Cu joining. It will discuss the various under-bump metallurgy (UBM) fabrication methods (electroplating, electroless plating and sputtering) and solder depositions methods (electroplating, ball drop, IMS, and solder screening). The course will cover the various failure modes related to bumping, such as barrier consumption, Kirkendall void formation, non-wets, BEOL dielectric cracking, electromigration, etc.
Biography: Dr. Shengmin Wen is the Principal Package Architect at Synaptics Inc., has more than 20 years of semiconductor industry experience in the areas of Si fabrication technology, advanced packaging and assembly process development, Si and packaging co-design, semiconductor device failure analysis, reliability and qualification, product engineering, testing, and volume production business management. Recent years, he focused on chip scale package (CSP) including wire bond, flip chip, wafer level Fan-In and Fan-out, and panel level packaging development. In particular, he has extensive and unique experiences in flip chip assembly technologies that uses fine pitch Cu Pillar bump with both mass reflow and thermal compression processes. He is an expert in package warpage control, substrate technologies, advanced fine pitch flip chip assembly process, and reliability.
He previously worked at Amkor Technology where he was a director of 3D CSP Product Group. Dr. Wen received his Ph.D. from Northwestern University, Evanston, IL, USA, researching on fatigue and reliability of electronic materials, where he created and published a science-based fatigue theory. Dr. Wen has been actively participating and contributing to industry technical conferences to learn, to share, and to contribute.
Eric Perfecto has over 39 years of experience working in the development and implementation of C4 and advanced Si packages at IBM and GLOBALFOUNDRIES. Responsibilities included UBM and Pb-free solder definition for C4 and u-Pillar interconnect, and yield improvements in C4 and 3D wafer finishing. He is currently working at the IBM Nanotech Center. He holds a M.S. in Chemical Engineering from the University of Illinois and a M.S. in Operations Research from Union College. Eric has published over 75 external papers, including two best Conference Paper Awards (2006 ESTC and 2008 ICEPT-HDP) and the 1994 Prize Paper Award from CMPT Trans. on Adv. Packaging. He holds 55 US patents and has been honored with two IBM Outstanding Technical Achievement Awards and an IBM Outstanding Contribution Award for the Development of 3D Wafer Finishing Process (2014). Eric was the 57th ECTC General Chair in Reno, NV, and the Program Chair at the 55th ECTC.
Eric is an IEEE Fellow and has achieved senior member status from IMAPS and Society of Plastic Engineers. He is an EPS Distinguish Lecturer, the Awards Program Director and elected board member of the Electronics Packaging Society of IEEE.
PDC 5: ESD Impact and Risk on IC Package Technology Development and MEMs Devices
Instructor: Charvaka Duvvury, ESD Consultant, IEEE Distinguished Lecturer
Course Objective: ESD has been a pervasive issue for semiconductor IC technologies for the last four decades. However, CMOS technology scaling and demand for ultra-high-speed IOs are placing a severe restriction on achieving adequate reliability from the ESD threat. IC package development is in the center of this growth towards ICs with high-speed applications. The ESD discharge coming from the Charged Device Model (CDM) is not only the most critical but is also strongly package design dependent and advances in package technology development need to be understood to mitigate ESD threat. Combining now with the recent trends in 3D IC integration an increasing awareness on the impact on ESD is needed. In parallel, with applications in MEMs devices, ESD design strategy is also facing an important design issue for safe applications. This tutorial will first review the physics of CDM and its relative dependence on different IC package types as well as how the IC package advances are making it challenging for ESD reliability. Some examples of IC package modeling to predict CDM discharge levels that depend on package types including WSP devices will be covered. Some insight into heterogeneous packages that will influence ESD will be given. Finally, the presentation will also address new innovative and promising areas of ESD protection through interposer integration for ESD protection.
Biography: Dr.Charvaka Duvvury received his PhD in Engineering Science from the University of Toledo and has worked for Texas Instruments for 35 years in semiconductor device physics with development work in ESD design. He was elected as TI Fellow in 1997 and as IEEE Fellow during 2008. He has contributed to the industry by offering tutorials at various IEEE sponsored conferences, and is an active participant in the EDS DL Program. He served as an editor for TDMR (2001-2011) and is currently serving as editor for TED. After retiring from TI, he has been working as a technical consultant on ESD design. He is a recipient of the IEEE Electron Devices Society’s Education Award (2013), Outstanding Contributions Award from the EOS/ESD Symposium (1990), and Outstanding Industry Mentor Award from the Semiconductor Research Council (1994 and 2012). From 2004-2006 he served on the IEDM CMOS Reliability Sub-committee. He has published over 150 papers in technical journals and conferences and holds US 75 patents. He co-authored and contributed to 5 books. Charvaka has been serving on the Board of Directors of the ESD Association (ESDA) since 1997 promoting ESD education and research at academic institutes. He served twice as General Chairman of the ESD Symposium. He has been co-founder and co-chair of the Industry Council on ESD since 2006. During 2015 he became a co-founder of the iT2 Technologies that utilizes an intelligent software engine for rapid ESD data analysis.
EPTC 2021 Platinum Sponsor
Y. P. Zhang
John H Lau