Packaging at the Emerging Edge

Abstract:

The connected world is exploding with new features and capabilities in every imaginable device. This trend is expected to continue for the foreseeable future with artificial intelligence and machine learning increasingly impacting devices and applications. How the devices will be architected and packaged is a challenge for engineers today and into the future. Housed far from data centers, edge devices reside in active environments, are highly power, thermal, and cost sensitive, and leverage diverse functions and semiconductor technologies. Thus, they drive the need for new and differentiated packaging and heterogenous integration technologies to support them. The keynote will explore these emerging market and technology dynamics, providing relevant examples.

Speaker’s Biography

Glenn G. Daves is Senior Vice President of Package Innovation at NXP Semiconductors. He is responsible for package design, package technology development, and assembly process development in support of NXP’s full product portfolio. Prior to its acquisition by NXP, Glenn led packaging and printed circuit board development for Freescale Semiconductor. Prior to that, he led global packaging product and technology development at the IBM Corporation. He has also held leadership positions in project management, test and burn-in engineering, and assembly manufacturing engineering. Glenn holds twenty-seven U.S. patents and has degrees from Brown University, the University of Illinois at Urbana-Champaign, and Alliance Theological Seminary. He serves on the National Leadership Council of World Vision U.S. 

 Tectonic forces shaping the future of the semiconductor industry

Abstract

As we confidently raced into the second decade of this millennium, we were oblivious to what lie ahead.  Just three months in, our world rapidly transformed in unprecedented ways.  With disbelief, frustration, and heartbreak, our entire civilized world was reconfigured before our eyes. The COVID-19 pandemic affected all of us in ways that were nearly impossible to imagine before our lives and industries were forever altered.  Semiconductors were perhaps the most impacted of all where our world’s awareness of ‘chips’ being made from potatoes gave way to nearly universal understanding that silicon chips are of utmost importance in our daily lives.  A tiny, spiked module of just 100nm in size was at the core of the transformation.  The pandemic was just one of several powerful forces that are reshaping semiconductor supply chains, electronic systems architectures and device design.  In this address, we’ll examine our current landscape as well as the technological and geopolitical forces that are shaping the future of the semiconductor industry.

Speaker’s Biography

Tim Olson is founder, CEO and a director of Deca Technologies, Inc. or Deca.  Tim has served in both CEO and CTO roles as Deca established its industry leading M-Series™ fan-out and Adaptive Patterning® technologies. Tim previously served as Sr. Vice President of Global Research & Development and Emerging Technologies at Amkor where he led global R&D driving the industry’s first fine pitch Cu pillar flip-chip and POP TMV technologies from idea to high volume production. Prior to Amkor, Tim was EVP of Products and Operations at Micro Component Technology where strip test technology went from the drawing board to an industry-leading approach in terms of productivity, quality and cost. Tim started his career in semiconductors at Motorola where he led creation of PRISM, an advanced assembly and test CEO model factory, which delivered two major innovations to the semiconductor industry:  strip-based final test and 2D codes borrowed from NASA for product tracking and traceability. Tim graduated magna cum laude from UND with bachelor’s degrees in mechanical engineering and engineering management. He recently received the prestigious Founder’s Award from IMAPS. Tim holds over 30 issued patents relating to packaging, software, equipment, process, and design.             

  Breaking Boundaries of IC Packaging through Innovative Integration Technology

Abstract

The hot demand by generative AI brings lots of requirement for chip design and packaging assembly. The chip design is transformed from monolithic to chiplet. The computing platform is transformed into highly interconnected system in cluster. Data processing in high bandwidth, low latency and high performance is a must. By enabling the chiplet technology, more compute and memory tiles would be crammed into the limited area. The denser and shorter interconnect with lower resistance will be implemented. In the meantime, the chip module and package size is growing in a fast pace beyond imagination. In this speech, I would provide a comprehensive introduction on different packaging types with its own applications, and characteristics analysis on several aspects such as design, thermal, warpage, electrical and more. In addition, the challenges and solutions will be reviewed. Last but not least, the recent developments of Co-Packaged Optic for optimizing efficiency of data transmission will be addressed as well.

Speaker’s Biography

Dr Yu-Po Wang is Vice President of R&D Center, SPIL Yu-Po Wang received Ph.D. in Mechanical Engineering from Binghamton University, State University of New York , U.S.A. In 1997, he started career at Gintic Institute of Manufacturing Technology in Singapore. He joins SPIL in 1998 and leads the R&D Package Application and Technology Support Team in substrate/package design, material characterization and advanced package. Dr. Wang has strong knowledge and experience in packaging characterization including thermal/ electrical simulation, advanced material(co-development), design and advanced packaging development. He has over 83 patents in US.