Unleashing AI Power:

The Hybrid Copper Bonding Technology for 3D System Integration, HBM, and CPO

With the rapid increase in demand for High Performance Computing (HPC), 3D IC technology is particularly impactful in high-performance computing, where the demand for extreme processing power and efficiency is paramount. Hybrid Cu Bonding (HCB) technology allows two advanced logic or memory devices to be stacked directly on top of each other, allowing for ultra-dense (and ultra-short) connections between the two chips, and is primarily aimed at high performance parts. Besides, face-to-back or face-to-face is relative to more careful floor planning, through-silicon via (TSV) management, and process challenging considerations are required. High Bandwidth Memory (HBM) are expected to grow by two to three times per generation due to the bandwidth and capacity required for HPC. The power of the next generation of HBM is anticipated to exceed 30W, and the number of HBM4 stacks will reach up to 16, potentially leading to higher thermal resistance than the required thermal standard. HCB technology represents the most promising solution for improved heat dissipation in HBM packages, as it eliminates the need for epoxy materials and offers a higher density of I/O metals at the interface. However, several obstacles must be overcome to demonstrate 16 stacks of HBM core chips on a buffer wafer. Key issues for HBM4 with 16H include the control of thin chip warpage, and surface topology, which are the main causes of HCB interface void and delamination. 

In additional, the use of HCB for a high-bandwidth and energy efficient optical link for 2.5D/3D system integration is a promising future trend, and its application in CPO technology is also anticipated in near future. In this presentation will provide an in-depth analysis of merits and challenges of HCB technology for 3DIC, HBM and CPO applications.

Speaker’s Biography

Vic J. C. Lin received the Ph.D. degree in 1999, and he joined TSMC where he built his experience in BEOL process, FEOL knowledge and reliability capability until 2009. He was as an assignee, with SEMATECH (US/Austin) in 2001, and with IMEC (Belgium) from 2007 to 2009.  After completed IMEC assignment, he started working on advanced packaging development, he pioneered wafer-level-system integration technologies, including 3DIC/TSV, CoWoS, and InFO until to end of 2017.

Vic Joined Micron in Jan. 2018, and he was the Sr. Director and RD head of Micron Taiwan that in charge of advanced packaging technology development. He quickly established the RD team and RD pilot line of 3DIC advanced packaging and enable DDR5 w/ TSV stacking and HBM2E which is the first 8-layer memory stacking technology in Taiwan and for Micron.

He joined a startup company Skytech be a CEO and was leading this local equipment vendor during 2019/09~2022/10 to develop a variety of PVD/ALD/Bonder/De-bonder product portfolios for advanced packaging, LEDs, IGBTs, MOSFETs, and AlCu/TTN.

Now he is Corporate EVP of Samsung Electronics which in charge of advanced packaging development for 3DIC, HBM and CPO.

He has authored or coauthored over 40 journal or conference papers. He holds >500 US patents.

Packaging at the Emerging Edge

Abstract:

The connected world is exploding with new features and capabilities in every imaginable device. This trend is expected to continue for the foreseeable future with artificial intelligence and machine learning increasingly impacting devices and applications. How the devices will be architected and packaged is a challenge for engineers today and into the future. Housed far from data centers, edge devices reside in active environments, are highly power, thermal, and cost sensitive, and leverage diverse functions and semiconductor technologies. Thus, they drive the need for new and differentiated packaging and heterogenous integration technologies to support them. The keynote will explore these emerging market and technology dynamics, providing relevant examples.

Speaker’s Biography

Glenn G. Daves is Senior Vice President of Package Innovation at NXP Semiconductors. He is responsible for package design, package technology development, and assembly process development in support of NXP’s full product portfolio. Prior to its acquisition by NXP, Glenn led packaging and printed circuit board development for Freescale Semiconductor. Prior to that, he led global packaging product and technology development at the IBM Corporation. He has also held leadership positions in project management, test and burn-in engineering, and assembly manufacturing engineering. Glenn holds twenty-seven U.S. patents and has degrees from Brown University, the University of Illinois at Urbana-Champaign, and Alliance Theological Seminary. He serves on the National Leadership Council of World Vision U.S. 

 Tectonic forces shaping the future of the semiconductor industry

Abstract

As we confidently raced into the second decade of this millennium, we were oblivious to what lie ahead.  Just three months in, our world rapidly transformed in unprecedented ways.  With disbelief, frustration, and heartbreak, our entire civilized world was reconfigured before our eyes. The COVID-19 pandemic affected all of us in ways that were nearly impossible to imagine before our lives and industries were forever altered.  Semiconductors were perhaps the most impacted of all where our world’s awareness of ‘chips’ being made from potatoes gave way to nearly universal understanding that silicon chips are of utmost importance in our daily lives.  A tiny, spiked module of just 100nm in size was at the core of the transformation.  The pandemic was just one of several powerful forces that are reshaping semiconductor supply chains, electronic systems architectures and device design.  In this address, we’ll examine our current landscape as well as the technological and geopolitical forces that are shaping the future of the semiconductor industry.

Speaker’s Biography

Tim Olson is founder, CEO and a director of Deca Technologies, Inc. or Deca.  Tim has served in both CEO and CTO roles as Deca established its industry leading M-Series™ fan-out and Adaptive Patterning® technologies. Tim previously served as Sr. Vice President of Global Research & Development and Emerging Technologies at Amkor where he led global R&D driving the industry’s first fine pitch Cu pillar flip-chip and POP TMV technologies from idea to high volume production. Prior to Amkor, Tim was EVP of Products and Operations at Micro Component Technology where strip test technology went from the drawing board to an industry-leading approach in terms of productivity, quality and cost. Tim started his career in semiconductors at Motorola where he led creation of PRISM, an advanced assembly and test CEO model factory, which delivered two major innovations to the semiconductor industry:  strip-based final test and 2D codes borrowed from NASA for product tracking and traceability. Tim graduated magna cum laude from UND with bachelor’s degrees in mechanical engineering and engineering management. He recently received the prestigious Founder’s Award from IMAPS. Tim holds over 30 issued patents relating to packaging, software, equipment, process, and design.             

Breaking Boundaries of IC Packaging through Innovative Integration Technology

Abstract

The hot demand by generative AI brings lots of requirement for chip design and packaging assembly. The chip design is transformed from monolithic to chiplet. The computing platform is transformed into highly interconnected system in cluster. Data processing in high bandwidth, low latency and high performance is a must. By enabling the chiplet technology, more compute and memory tiles would be crammed into the limited area. The denser and shorter interconnect with lower resistance will be implemented. In the meantime, the chip module and package size is growing in a fast pace beyond imagination. In this speech, I would provide a comprehensive introduction on different packaging types with its own applications, and characteristics analysis on several aspects such as design, thermal, warpage, electrical and more. In addition, the challenges and solutions will be reviewed. Last but not least, the recent developments of Co-Packaged Optic for optimizing efficiency of data transmission will be addressed as well.

Speaker’s Biography

Dr Yu-Po Wang is Vice President of R&D Center, SPIL Yu-Po Wang received Ph.D. in Mechanical Engineering from Binghamton University, State University of New York , U.S.A. In 1997, he started career at Gintic Institute of Manufacturing Technology in Singapore. He joins SPIL in 1998 and leads the R&D Package Application and Technology Support Team in substrate/package design, material characterization and advanced package. Dr. Wang has strong knowledge and experience in packaging characterization including thermal/ electrical simulation, advanced material(co-development), design and advanced packaging development. He has over 83 patents in US.    

Advanced Packaging – Customization trends and Standardization opportunities .

This keynote talk while addressing the recent advancements and challenges in advanced packaging technologies will point towards to the increasing customization trends.  These customizations are happening in advanced packaging technologies for HPC/AI, 5G/6G, IoT and Power electronics for various market segments such as Data Center, mobile and communication networks , automotive, industrial applications.  

The talk will bring out several examples of customization trends in Advanced heterogenous integrated packaging and will discuss the pros and cons.

The advantages of standardization in terms of quality, reliability and scalability in  manufacturing are challenged with the increasing trends in customization. Some of the standardization opportunities will also be discussed during the talk.

Speaker’s Biography

Devan (Mahadevan) Iyer Ph.D  is a Chief Strategist - Advanced Packaging at IPC International Inc.  Prior to joining IPC in March this year, he was Senior Vice President managing business units at Amkor Technologies and a Corporate Vice President at Texas Instruments where he was  leading TI’s worldwide advanced packaging, assembly engineering organizations. Devan has also led Packaging R&D organization at Institute of Microelectronics (IME) Singapore and as a Research director led advanced packaging research and industry consortia at Georgia Tech Packaging Research Center.  Devan has more than 200 publications and 35 patents to his credit.

Strategic Directions for Electronics Packaging

Recent advances in electronics packaging have come to the rescue as CMOS scaling has stalled making possible the incredible advances in Artificial Intelligence and Machine Learning that promise to transform our lives. This journey, however, has only just begun and much more is yet to come. The key features that will drive this transformation can be described with the simple strategy of “scale-down and scale-out” that has characterized monolithic CMOS scaling for several decades, the drive to chiplets with higher yields, and the ability to assemble a diversity of technologies on the same substrate allowing us to blur the lines between monolithic chip and a large heterogeneous assembly of chips. While, we have made progress towards this goal, the technologies we have developed have ridden on legacy packaging technologies making such systems incredibly complex and expensive to build. In this talk we will describe our approach to simplify packaging at all levels: from design, architecture, process and manufacturing that have the potential to take packaging to the next level including the ability to scale packaging systematically. There are many challenges in this approach. In this talk we will outline these challenges and show that the adoption of silicon like technology, new cooling and power delivery approaches as well as design enablement will propel packaging into the next dimension.

Speaker’s Biography

Subramanian S. Iyer (Subu) is Distinguished Professor and holds the Charles P. Reames Endowed Chair in the Electrical Engineering Department and a joint appointment in the Materials Science and Engineering Department at the University of California at Los Angeles. Till recently, he was on assignment to the US Department of Commerce as Director of the National Advanced Packaging Manufacturing Program, where he laid the foundational strategy for the national packaging imperative. He is the founding Director of the Center for Heterogeneous Integration and Performance Scaling (UCLA CHIPS). Prior to that he was an IBM Fellow. His key technical contributions have been the development of the world’s first SiGe base HBT, Salicide, electrical fuses, embedded DRAM and 45nm technology node used to make the first generation of truly low power portable devices as well as the first commercial interposer and 3D integrated products. Since joining UCLA, he has been exploring new packaging paradigms and device innovations that may enable wafer-scale architectures, in-memory analog compute and medical engineering applications.   He is a fellow of IEEE, APS, iMAPS and NAI as well as a Distinguished Lecturer of IEEE EDS and EPS. He is a Distinguished Alumnus of IIT Bombay and received the IEEE Daniel Noble Medal for emerging technologies in 2012 and the 2020 iMAPS Daniel C. Hughes Jr Memorial award and the iMAPS distinguished educator award in 2021. Prof. Iyer was also Prof. Ramakrishna Rao Visiting Chair Professor at IISc, Bengaluru.