Fundamental Understanding of Hybrid Bonding Mechanism By Utilizing Molecular Dynamics Simulation Approach 

Dr. Minwoo Rhee, Samsung

Abstract

Hybrid bonding has emerged as a promising 3D integration technology for the next generation stacking devices, with the advantages of higher performance and smaller form factor over the conventional micro-bump interconnects. The overall procedures of hybrid bonding that encompass plasma surface treatment, hydration, bonding and annealing are all important steps for successful integration, but detailed mechanisms underlying each process step have not been fully elucidated yet, especially at the atomic level bonding interfaces. Here, we present atomistic-scale modeling procedures of SiO2 and SiCN thin film which are the dielectric materials actively investigated for Cu/dielectrics hybrid bonding applications. The surface models we developed in this work reflect important surface features such as atomic compositions, oxide thickness, surface roughness from various experimental characterization techniques. Reactive molecular dynamics (MD) simulations were then carried out on these models to demonstrate hybrid bonding of dielectric materials and elucidate the surface activation to bonding mechanisms. The plasma-surface interactions of dielectric surfaces presented in our work provide thorough understanding of plasma activated surface topology at the resolution scale that is often hard to reach with the experimental characterization techniques. In addition, the computational workflow represented here may provide a useful guideline for the surface modification process and overcome the time and expense resource constraints by supplementing empirical decisions made from the trial and error based full design of experiment endeavors.

Biography

MINWOO RHEE is Master and Vice President of Technology and leading Packaging Technology Development Lab. in Manufacturing Technology R&D center in Samsung Electronics since 2015. He received the B.Eng., M.S., and Ph.D. degrees in chemical engineering from Sogang University, Seoul, in 1996, 1998, and 2010, respectively and also received Master's degree of management of technology from National University of Singapore (NUS) in 2017. He has been working for more than 23 years in microelectronics packaging research and development for both industry and research institutes and also has extensive experiences in new packaging and material development, numerical modeling, and characterization. From 1999 to 2010, he was with research and development at Amkor Technology, where he was the senior manager and leader of the material characterization, modeling and failure analysis group and resolved lots of chronicle failures and quality issues with worldwide semiconductor companies. Dr. Rhee was a recipient of “the Best Employee of the Year Award in 2009 at Amkor (in R&D section)”. Also he was with the research and development group at Fairchild Semiconductor as a principal engineer, where he developed power device packaging solutions such as automotive three-phase inverter module for high-power electronics, which were successfully applied for mass production for automotive industries. From 2011 to 2015, he was the head of department of IPP (interconnection and packaging program) at Institute of Microelectronics (IME-A*STAR), Singapore and led the advanced packaging group and related industry consortium projects for semiconductor, automotive, oil and gas, deep sea exploration, and aerospace industries. At IME A*STAR he had project-leading experiences of lots of public-funded and industry projects related with material and new packaging development such as MEMS, 3DIC TSV packaging, and power electronics packaging solution for SiC/GaN devices. He is currently Master and vice president of technology and leading advanced packaging equipment research and development in Mechatronics Research, Samsung Electronics since 2015. Dr. Rhee is recipient of the "Future Creator Award" and "DS (Device Solution) Excellence in Technology Award" from Samsung Electronics in 2018. He has authored and co-authored more than 80 journal and conference papers and about 30 patents in microelectronics materials and packaging fields.

Path Finding to Maximization of AI/HPC/GPC System Performance

Dr. Gamal Refai-Ahmed, AMD

Abstract

This paper will deliver path finding to maximize AI/HPC system performance from thermo-mechanical prospective. In this article the challenges that emerges to develop continuous innovations manufacturable products will be explained. These challenges are utilizing the opensource ecosystem standard; Sticking to a standard that doesn’t evolve rapidly can impact the design freedom; the package architecture, intended application, system level, and manufacturing solution impact on the performance and system IT load balancing. To address these challenges and to push the boundary, a strategy/roadmap and a pathfinding will be presented. Furthermore, this study will be disclosing key factors which need to be considered in developing present and next generation of thermo-mechanical solutions. These factors are: enabling and working on/around manufacture infrastructure, accommodating future heterogeneous integration, utilizing current/future infrastructure of board level manufactured assembly, addressing the solution from system level, extending air cooling, enabling liquid cooling, and considering immersion liquid cooling. Based on these factors, a Path finding strategy will be built on four elements/pillars which are hosting facilities, driving ecosystems, defining cost based on operating condition and reliability, and synergistic management of workload in both IT equipment and cooling systems.

Biography

Dr. Gamal Refai-Ahmed, Life Fellow ASME, Fellow IEEE, Fellow Canadian Academy of Engineering, Professional Engineer Ontario, EPS IEEE Distinguished Lecture, is AMD Senior Fellow.  He obtained the Ph. D. degree from the University of Waterloo. He has been recognized as one of the global technical leaders through his numerous publications (more than 120 publications) and patents& patents pending US (more than 65) and International (more than 110). His contributions are clearly seen in several generations of both GPU, CPU and FPGA for HPC, AI, ML, NIC, Game Console, Aerospace& Defense and Telecom products. In 2015, Gamal was tasked to  initiate the heterogeneous integration of system level power, thermal, mech and assembly with package and Si development in first initial planning.  He has been a key player to introduce all Alveo products and high-end Si  CoWos, InFo, Chiplets  PKG  to AMD Customers. He was behind the introduction of the first Lidless FPGA   20, 16, 7nm technology nodes with highest warpage in mass production in  Alveo products, and its Telecom, AI, HPC customers (e.g. MSFT, AWS, Nokia, Cisco and A&D).  his developed strategy of technology enable AMD FPGA  products to outperform the Intel/Altera Products. Gamal is the recipient of 2008 excellent thermal management award, 2010 Calvin Lecture and 2013 K16- Clock award in recognition for his scientific contributions and leadership of promoting best electronics packaging engineering practice. In 2014, Gamal received the IEEE Canada R. H. Tanner Industry Leadership for sustained leadership in product development and industrial innovation. In 2016, ASME awarded Gamal the ASME Service Award. State University of New York, Binghamton University awarded him the Innovation Partner Award for his industrial role with Binghamton University. In continuation to Dr Refai contributions to the best engineering practice, State University of New York at Binghamton awarded him the Presidential University medal in 2019 which is the highest recognition honor by the university.  In 2021, Gamal was elected to IEEE Fellow and  EIC Fellow.

Room Temperature Bonding Technology - Surface Activated Bonding for 3D and Heterogenous Integration

Prof. Tadatomo Suga , University of Tokyo

Abstract

The surface activated bonding (SAB) method is based on surface activation concept which is realized by energetic particles bombardment in ultra-high vacuum to clean and activate the surfaces so that they can be bonded very strongly at room temperature without any heat treatment. Recently the standard SAB method was modified and applied successfully to heterogeneous semiconductor wafer bonding and 3D integration. This presentation will review the current status of the SAB method for volume productions, and describe the future directions including recent R&D results for heterogeneous integration of semiconductor 3D device and power devices.

Biography

Tadatomo SUGA joined the Max-Planck Institut für Metallforschung in 1979, obtained his Ph.D. degree in materials science from University of Stuttgart in 1983. Since 1984 he has been a faculty member of the University of Tokyo, and has been a professor in the Department of Precision Engineering of the School of Engineering since 1993. He has been also the Chair of IEEE CPMT Society Japan Chapter, and the President of the Japan Institute for Electronic Packaging, as well as the Chair of JSPS University-Industry Cooperative Research Committee for Innovative Interface Bonding Technology. His research focuses on microelectronics and microsystems packaging, and development of key technologies related to low temperature bonding and interconnects. In the Marich of 2019, he retired from the University of Tokyo, being Professor Emeritus, and joined Meisei University to continue his research work.

Submicron Nanosecond Thermoreflectance Imaging for Thermal and Failure Analysis

Dr. Mo Shakouri, Microsanj

Abstract

Performance requirements for today’s semiconductor devices are leading to shrinking geometries, new materials, and more complex structures. Additionally, devices are being deployed in mission-critical applications ranging from 5G, 6G, and Smart Grid networks, to automotive and defense electronics. Devices may also be required to operate in a challenging thermal environment. High temperatures, hot spots and temperature spikes can have a major impact on reliability. Since high temperatures contribute to MTTF, it is essential that one have a thorough understanding of static and dynamic thermal performance. Fortunately, advancements in characterization techniques are making it easier to gain this understanding to ensure reliability while meeting challenging performance requirements.

Biography

Dr. Mo Shakouri is co-founder, President & CEO of Microsanj LLC, a leading supplier of high resolution, thermal imaging systems designed to address the thermal challenges faced by today’s advanced device designers.  Dr. Shakouri received his PhD from Stanford University and has more than 20 years of experience directing major programs with Hewlett-Packard Corporation, Lucent Technologies, and Alvarion Corporation prior to the founding of Microsanj in 2007. Mo Shakouri also serves as CEO for Telewave.io and is the Board Chairman for the WiMAX Forum.

Advanced Fan-Out Packaging for Chiplet Integration

Dr. Yu-Po Wang, SPIL

Abstract

Due to massive volume of data growth in recent years, increasing number of applications appears on the market to fulfill data manipulation demands in several aspects such as data collection, transmission, storage and calculation. In contrast, the advance of transistor density per area on wafer is getting slower and more expensive to manufacture. Costly large monolithic chip with high-end process node in traditional way is no longer the ideal choice nowadays. With the help of advanced packaging technology, it is capable of integrating memories and chiplets in different process nodes, functions and die sources into a single package. All in all, chiplet solution in advanced packaging might be the optimal answer to the difficulties encountered today.

Biography

Yu-Po Wang received Ph.D. in Mechanical Engineering from Binghamton University, State University of New York , U.S.A. He joins SPIL in 1998 and leads the R&D Package Application and Technology Support Team in substrate/package design, material characterization and advanced package. Dr. Wang has strong knowledge and experience in packaging characterization including thermal/ electrical simulation, advanced material(co-development), design and advanced packaging development. He has over 83 patents in US.

Hybrid Bonding – State-of-the-Art and Upcoming Requirements in W2W and D2W

Dr. Bernd Dielacher, EVG

Abstract

Even though heterogeneous integration is not new to the industry, the packaging aspect has not been the focus on any of the PPAC metric. In recent years the system performance is getting more important, where heterogeneous integration and system-technology co-optimization (STCO) are the key building blocks for future devices, especially in high performance, AI and mobile applications. The presentation will give a short outlook into the session, including key building blocks of technology.

Over the last decade fusion and hybrid bonding on wafer level has developed and is now readily available as unit process in most foundry and device manufacturers worldwide. In the current industry transformation away from optimization on planar devices towards system integration and towards 3D stacked devices, bonding technologies are playing a crucial role. While most devices such as image sensors or stacked memory have been designed specifically for 3D integration and bonding, the next technology transformation as a universal high density interconnect technology will also trigger a new integration process. Therefore, wafer-level as well as die-level hybrid bonding technologies are being developed and depending on interconnect density, chip size, system yield and cost, the best fit in terms of integration flow will be selected.

In this presentation we will provide an overview on the current industry trends and technological developments both for wafer-to-wafer as well as die-to-wafer hybrid bonding. Key technology differentiators, integration scenarios are discussed with respect to the hybrid bonding schemes in wafer to wafer-as-well as die-to-wafer integration. In addition, we will report on developments for IR release carriers in the scope of hybrid bonding.

Biography

Dr. Bernd Dielacher is business development manager at EV Group (EVG) where he evaluates global market trends and develops growth opportunities for EVG's bonding, lithography and nanoimprint businesses with a particular focus on the MEMS and biomedical technology market. Bernd holds a master’s degree in Microelectronics from Vienna University of Technology and received a PhD in Biomedical Engineering from ETH Zurich.

1.  Fundamental Understanding of Hybrid Bonding Mechanism By Utilizing Molecular Dynamics Simulation Approach – Minwoo Rhee (Samsung)

2. Path Finding to Maximization of AI/HPC/GPC System Performance – Gamal Refai-Ahmed (AMD)

3. Room Temperature Bonding Technology - Surface Activated Bonding for 3D and Heterogenous Integration – Tadatomo Suga (University of Tokyo)

4. Submicron Nanosecond Thermoreflectance Imaging for Thermal and Failure Analysis – Mo Shakouri (Microsanj)

5. Advanced Fan-Out Packaging for Chiplet Integration – Yu-Po Wang (SPIL)

6. Hybrid Bonding – State-of-the-Art and Upcoming Requirements in W2W and D2W – Bernd Dielacher (EVG)