Professional Development Courses (PDC), Special Programs and Highlights of EPTC 2018
Introduction to Fan-out Wafer Level Packaging
Dr. Beth Keser
Director, Packaging Engineering, Intel Corporation
Advanced Integrated Circuit Design for Reliability
Dr. Richard Rao
Fellow, Microsemi Corp, USA
3D SIP For ASIC and DRAM Integration
Dr. Li Li
Distinguished Engineer, Cisco Systems Inc
Understanding Flip Chip Technology and Its Applications
Mr. Eric Perfecto
Principal Member of the Technical Staff, GLOBALFOUNDRIES
Introduction to 3D Interconnect and Packaging Technologies
Prof. Sarah Kim
Seoul National University of Science and Technology
Power Electronic Packaging Reliability, Materials, Assembly and Simulation
1. Dr. Ning-Cheng Lee, Vice President of Technology, Indium Corporation
2. Dr. Yong Liu, Principal Member of Tech Staff, ON Semi
3. Prof. Sheng Liu, Dean of the School of Power and Mechanical Engineering and the Institute of Technological Science of Wuhan University
Details of PDC speakers
PDC 1: INTRODUCTION TO FAN-OUT WAFER-LEVEL PACKAGING
Course Leader: Dr. Beth Keser – Intel Corporation
Fan-out wafer level packaging (FO-WLP) technologies have been developed across the industry over the past 15 years and have been in high volume manufacturing for over 8 years. FO-WLP has matured enough that it has come to a crossroads where it has the potential to change the electronic packaging industry by eliminating wire bond and bump interconnections, substrates, leadframes, and the traditional flip chip or wire bond chip attach and underfill assembly technologies across multiple applications. This course will cover the advantages of FO-WLP, potential application spaces, package structures available in the industry, process flows, material challenges, design rule roadmap, reliability, and benchmarking.
1. Current Challenges in Packaging
2. Definition and Advantages
4. Package Structures
6. Material Challenges
7. Equipment Challenges
8. Design Rule Roadmap
Who Should Attend:
Engineers and managers responsible for advanced packaging development, package characterization, package quality, package reliability and package design should attend this course. Suppliers who are interested into supporting the materials and equipment supply chain should also attend. Both newcomers and experienced practitioners are welcome.
BETH KESER, Ph.D., a recognized global leader in the semiconductor packaging industry with over 20 years of experience, received her B.S. degree in Materials Science and Engineering from Cornell University and her Ph.D. from the University of Illinois at Urbana-Champaign. Beth’s excellence in developing revolutionary electronic packages for semiconductor devices has resulted in 27 patents and patents pending and over 40 publications in the semiconductor industry. For over 7 years, Beth led the Fan-Out and Fan-In Wafer Level Packaging Technology Development and NPI Group at Qualcomm where she and her team qualified over 50 products resulting in over 8 billion units shipped--technology consumers around the world enjoy in cell phones today. Beth is also an IEEE EPS Distinguished Lecturer who chaired IEEE EPS’s 2015 ECTC and is currently EPS's VP of Education. Based in Munich, Germany, Beth currently leads the Components and Systems Solutions Department at Intel Corporation in the Communication Device Group.
PDC 2: ADVANCED INTEGRATED CIRCUIT DESIGN FOR RELIABILITY
Course Leader: Dr. Richard Rao – Microsemi Corp, USA
This short course provides a holistic understanding of all aspects of reliability failure modes and mechanisms of an advanced IC product and the design for reliability methodology. It covers advanced Si process like FinFET, packaging technologies like Flip Chip BGA, Wafer Level packages, 2.5D/3D and interconnects like Cu pillar, TSV/uBumps and Cu/Cu hybrid bonding.
Reliability models and statistics
Advanced Si reliability issues
FinFET FEOL reliability
BEOL Cu/ELK reliability
BEOL and FEOL interactions
Advanced packaging technologies and reliability failure mechanisms
Advanced packaging technologies including FCBGA, WLP &2.5D/3D, etc
TSV/uBumps, Interposer, Cu Pillar and Cu/Cu bond Related Failures
Interconnect migration failure under combined electrical current, thermal mechanical stress and temperature changes
Chip to package interaction (CPI)
Quantitative CPI reliability
Chip Board Package Interaction
IC Design for Reliability
Reliability target and usage conditions
Reliability design rules
Design rule implementations
RICHARD RAO, Ph.D., is currently a Fellow of Microsemi Corp, a lead supplier of high reliability integrate circuit, located in southern California, USA and an elected Senior Member of IEEE. He is the present Chair of IEEE EPS (Electronics Packaging Society) Reliability Technical Committee. Dr. Rao is responsible for the corporate reliability and advanced packaging solutions. His focus is to find the advanced packages to meet the high performance, high reliability and high power semiconductor ICs; to study the new failure modes and mechanisms of cutting edge Silicon and packaging technologies as well as to develop design for reliability solutions for advanced circuits, packaging and chip to package interaction. He has a Ph.D. degree in solid mechanics of materials from the University of Science and Technology of China, the most prestigious university in China. Prior to joining Microsemi in 2004, Dr. Rao held various academic and technical positions in reliability physics and engineering. He was an associate professor at University of Science and Technology of China, a research fellow at Northwestern University, Evanston, IL, USA and a National Science and Technology Board Research Fellow in Singapore; and a principal engineer at Ericsson Inc. He has published over 30 papers on reliability physics and applications and a main contributor of several JEDEC standards. He is a technical committee member of IRPS (International Reliability and Physics Symposium) and ECTC (Electronics Component and Technology Conference). He is a frequent speaker to IRPS, ECTC, ISQED (International Symposium on Quality Electronics Design), ASME Symposiums and a keynote speaker to ICEPT and International Conf on System on Chip, etc. Dr. Rao has over 20 years’ hands on experience and knowledge in silicon to package to system integration such as HKMG and FinFET, high performance FCBGA/CSP, WLP, 2.5D/3D, chip to package to board interaction, board and system level reliability physics and applications. He has conducted professional development courses on advanced IC reliability to both industrial and academic worlds.
PDC 3: 3D SIP FOR ASIC AND DRAM INTEGRATION
Course Leader: Dr. Li Li – Cisco Systems, Inc.
With the change in traditional IC scaling cadence, there is growing interest in system optimization and differentiation through 3-dimensional System-in-Package (3D SiP) technology for broad market applications including Artificial Intelligence (AI), High Performance Computing (HPC), Networking, and Internet of Things (IoT). Concurrently packaging technologies have still to meet the cost, performance, form factor and reliability goals. In this short course, we will examine the role of emerging 3D SiP packaging platform for addressing the gap seen between the slowdown of Moore’s Law scaling and the ever-increasing system integration requirements. Systems based on 3D SiP technology have been developed for integrating high performance logic devices like Application-Specific Integrated Circuit (ASIC) and 3D High Bandwidth (HBM) Dynamic Random-Access Memory (DRAM) devices. We will review enabling packaging and interconnect technologies as well as new elements introduced by 3D SiP and potential risks to reliability of the final products. A detailed review on technology and component level qualification will be presented. It will then be followed by a few examples as case studies on board level reliability validation.
Li Li, Ph.D., is a Distinguished Engineer at Cisco Systems, Inc. where he leads an initiative on 3D IC integration and advanced packaging development. He has been with Cisco since 2004 and has over 20 years industry experience in IC packaging design, technology development and qualification.
Dr. Li has published several book chapters and over 80 technical papers in the field of microelectronics packaging. He is on the Board of Governors of IEEE Electronics Packaging Society and the Board of Directors of HDP User Group International (HDPUG), Inc.
He received his M.S. and Ph.D. degrees in Mechanical Science and Engineering from the University of Illinois at Urbana-Champaign.
3D SiP Introduction
Enabling Technologies for 3D SiP
3D Stackable Memory
High Density Interposer
i. Silicon Interposer
ii. Organic Interposer
3D SiP for ASIC and HBM DRAM Integration
Organic Interposer Design
Simulation and Results
3D SiP Assembly
- Test and Characterization
- Reliability Challenge
PDC 4: UNDERSTANDING FLIP CHIP TECHNOLOGY AND ITS APPLICATIONS
Course Leader: Mr. Eric Perfecto –GLOBALFOUNDRIES
This course will cover the fundamentals of flip chip fabrication and assembly processes. It will include all aspects of SnAgCu solder bumping and Cu Pillar technologies, comparison of various under bump and joining metallurgies and their intermetallics, and solder deposition methods. It will cover interconnect technologies used in single and multi-die assembly in organic laminate packages, wafer-level packages, embedded die, chip-on-chip, chip-on-wafer and 2.5D/3D flip chip packages as well as examples of leading industry application. Advanced and current trend of flip chip assembly process are provided briefly. This course will cover the failure types and the analytical tools, such as sonoscan, solder or die shear, x-section, x-ray, EBSD, and shadow or projection moiré used for process monitoring and to identify defect root cause. Failure modes, such as barrier consumption, Kirkendall and other solder voids formation mechanisms, contact non-wets, BEOL dielectric cracking, electromigration, etc. will be included dispersedly in course.
1. Introduction to Flip Chip Technologies
2. UBM Metal Selection and Solder Deposition Processes
3. C4 and Cu Pillar Fabrication Issues
4. Flip Chip Ball Grid Array (FCBGA) Assembly Process Flow
5. Chip Package Interaction and Electromigration
6. Flip chip technology new trends: Wafer Level, and 2.5D/3D
7. Substrate Technologies and Characterization Methods
Who Should Attend:
The targeted audience includes scientists, engineers and managers currently using flip chip technology (w/solder or Cu Pillar) or considering moving from wire bonding to flip chip, as well as reliability, product or applications engineers who need a deeper understanding of flip chip technologies: the advantages, limitations and failure mechanisms.
ERIC PERFECTO has 36 years of experience working in the development and implementation of advanced packages. He is currently Principal Member of the Technical Staff at GLOBALFOUNDRIES. He holds an M.S. in Chemical Engineering from the University of Illinois and an M.S. in Operations Research from Union College. Eric has published over 75 papers, holds over 45 US patents, He has been honored with two IBM Outstanding Technical Achievement Awards, one for the Development and Implementation of Multi-Level Thin Film Structures, and the second for Development and Implementation of 150 um pitch C4. He also received an IBM Outstanding Contribution Award for the Development of 3D Wafer Finishing Process. Eric was the 57th ECTC General Chair in Reno, NV, and the Program Chair at the 55th ECTC. He is an IEEE Fellow, a Distinguish Lecturer of the EPS society of IEEE, EPS BoG member and the current EPS Awards Program Director.
Eric’s recent areas of focus is the development and implementation of electroplated C4 and Cu pillars at GLOBALFOUNDRIES, and the assembly of Si photonics packages. His interest is in metallurgy effects on package reliability, design for manufacturability and yield improvements
PDC 5: INTRODUCTION TO 3D INTERCONNECT AND PACKAGING TECHNOLOGIES
Course Leader: Prof. Sarah Kim –Seoul National University of Science and Technology
3D interconnect and packaging technologies have been developed across the industries and universities over the past 20 years. 3D products with TSV (through Si via) have been in high volume manufacturing for over 5 years, which has the great potential to change the heterogeneous or high IO device packaging applications by improving power delivery, bandwidth, and latency and reducing a package size. This course will provide the introductory overview of 3D interconnect and packaging technologies. The technical trends and drivers, motivations, fabrication processes, stacking methods, benefits, and technical challenges will be discussed.
Technical trends and drivers
Core fabrication processes
TSV (through Si via)
Bonding (including Cu-to-Cu wafer bonding)
Yield (wafer level stacking)
Who Should Attend:
This course is intended for engineers who are new to this field, technical managers and scientific researchers who are interested in developing new technologies and products, and graduate students who are involved in advanced packaging process, design, and materials,
SARAH E. KIM, Ph.D., a professor at the Seoul National University of Science and Technology (Seoul Tech), received her B.S. in Materials Science and Engineering from Rensselaer Polytechnic Institute and her M.S. from Massachusetts Institute of Technology and her Ph.D. from Rensselaer Polytechnic Institute. Prior to join Seoul Tech, Sarah worked at Samsung Electronics, Intel, and Korea Institute of Science and Technology. In Intel she has worked on various areas of BEOL interconnect, 3D integration, and die-package interface development including liquid cooling, thick metal interconnect, and decoupling capacitor. Also, she led multiple wafer level package projects and managed a sort test group. At Seoul Tech, Sarah has been focusing her research on the development of 3D wafer packaging, fan-out wafer level packaging, and transparent oxide semiconductor. She holds more than 30 US patents including one of Intel's 45nm-node core patents and has numerous technical papers in international journals and received many honors and awards over the years (http://www.esl-seoultech.kr).
PDC 6: Power Electronic Packaging Reliability, Materials, Assembly and Simulation
Course Leaders: Dr. Ning-Cheng Lee – Indium Corporation, Dr. Yong Liu – ON Semiconductor Corp and Prof. Sheng Liu – Wuhan University
For power electronic devices, the die attach is primarily conducted with the use of high lead solder alloys. The reliability of the joints depends on the detailed design, particularly the UBM structure on the die side. On the other hand, the move toward lead-free has driven the introduction of Sn-based Pb-free solder alloys and Ag or Cu sintering materials. While the lead-free solder alloys may have a lower service temperature but a higher electromigration resistance, the sintering materials offer outstanding thermal and electrical conductivity, a and very high service temperature. In this course, those bonding materials will be introduced and discussed in detail.
Due to the intrinsic structural nature, the requirement for power product and its reliability is extremely high. This talk will present the overview of advances in power electronic packaging. A review of recent advances in reliability of power electronic packaging and modeling is presented based on the development of power electronics. The talk will cover in more detail of advanced modeling for reliability issues in both assembly manufacturing process induced reliability and the reliability tests. Along with power packaging development, the role of simulation in codesign and virtual prototype is a key to assure successful new power electronic packaging.
Modeling and simulation of microelectronic packaging and assembly is a multi-disciplinary activity that relies on the expertise of sequence dependent complex processes, almost all the material types, and detailed process windows; a very challenging task for both academic people and practicing engineers. The most popular methodology of design and manufacturing is called Design for X (DFX, here X refers to manufacturing, assembly, testing, reliability, maintenance, environment, and even cost). A packaging module and related application systems, like any other electronic systems, involve a lot of manufacturing processes from crystal growth, film deposition, etching, chip to wafer and wafer to wafer bonding, dicing/ sigulation, and extensive reliability testing for extended-life goals. Design procedure must be modified and DFX must be used so as to achieve prevention with integrated consideration of manufacturing processes, testing, and operation. The talk will focus on the many detailed processes in front end, back end, even probing, wire bonding, bonding, and so on. It covers the broad aspects from manufacturing to reliability, and to testing, with many examples. This talk can provide guidance to those in the field and present a design approach that must ultimately replace the build-test-fix-later process if the efficiencies and potential cost benefits of the microelectronic packaging systems are to be fully realized.
Ning-Cheng Lee, Ph.D. is the Vice President of Technology of Indium Corporation. He has been with Indium since 1986. Prior to joining Indium, he was with Morton Chemical and SCM. He has more than 30 years of experience in the development of fluxes and solder pastes for SMT industries. In addition, he also has very extensive experience in the development of underfills and adhesives. He received his PhD in polymer science from University of Akron in 1981, and BS in chemistry from Taiwan University in 1973.
Ning-Cheng is the author of “Reflow Soldering Processes and Troubleshooting: SMT, BGA, CSP, and Flip Chip Technologies” by Newnes, and co-author of “Electronics Manufacturing with Lead-Free, Halogen-Free, and Conductive-Adhesive Materials” by McGraw-Hill. He is also the author of book chapters for several lead-free soldering books. He received 1991 award from SMT Magazine and 1993 and 2001 awards for best proceedings papers of SMI or SMTA International Conferences, 2008 and 2014 awards from IPC for Honorable Mention Paper – USA Award of APEX conference, and 2010 Best Paper Award of SMTA China South Conference. He was honored as 2002 Member of Distinction from SMTA, 2003 Lead Free Co-Operation Award from Soldertec, 2006 Exceptional Technical Achievement Award from CPMT, 2007 Distinguished Lecturer from CPMT, 2009 Distinguished Author from SMTA, 2010 Electronics Manufacturing Technology Award from CPMT, 2015 IEEE Senior Member, 2015 Founder’s Award from SMTA, and 2017 IEEE Fellow. He has served on the board of governors for CPMT and SMTA board of directors. Among other editorial responsibilities, he serves as editorial advisory board of Soldering and Surface Mount Technology, Global SMT & Packaging and as associate editor for IEEE Transactions on Components Packaging Manufacturing Technology. He has numerous publications and frequently gives presentations, invited to seminars, keynote speeches and short courses worldwide on those subjects at international conferences and symposiums.
Dr. Yong Liu has been with ON Semiconductor Corp in South Portland, Maine since Sept, 2016 as a Principal Member of Tech Staff. Before Fairchild was acquired by ON Semiconductor, he worked at Fairchild Semiconductor as a Distinguished Member Technical Staff. His main interest areas are advanced analog and power electronic packaging, modeling and simulation, reliability and material characterization. He was elevated as IEEE fellow in 2015.
Sheng Liu, Ph.D. is the dean of the School of Power and Mechanical Engineering and the Institute of Technological Science of Wuhan University. He is the National Science Fund for Distinguished Young Scholars (Type B), Yangtze River Scholar Distinguished Professor, ASME Fellow, IEEE Fellow, and as a professionalism in the area of the “863 program” of the National High Technology Research and Development Program. He has acquired his doctor degree in Stanford University in 1992. From 1992 to 1995, he held the title of lecturer at Florida institute of technology. He was authorized as a tenure from 1995 to 2001 in the Department of Mechanical Engineering and manufacturing research at Wayne State university. During the period of his title job, his outstanding achievements in the research of the reliability of complex structure of IC packaging, he was granted the President’s prize of the United States of America. The research of IC and MEMS packaging with the research of CAD allowed him to obtain the Young Investigator Award in Natural Sciences of the United states of America. In 2001, Sheng Liu resigned from the Department of Mechanical Engineering and Manufacturing research at Wayne State University and returned to China, where he took the lead of carrying out research focusing on the theory of Reliable Engineering Development for electronic packaging.