The 15th Electronics Packaging Technology Conference (EPTC 2013) is an International event organized by the IEEE Reliability/CPMT/ED Singapore Chapter and sponsored by IEEE CPMT Society.

EPTC 2013 will feature technical sessions, short courses/forums, an exhibition, social and networking activities. It aims to provide a good coverage of technological developments in all areas of electronic packaging from design to manufacturing and operation. It is a major forum for the exchange of knowledge and provides opportunities to network and meet leading experts in the field.

Since its inauguration in 1997, EPTC has developed into a highly reputed electronics packaging conference in Asia and is well attended by experts in all aspects related to packaging technology from all over the world.

• Advanced Packaging: Flip-chip and wire-bond packaging, embedded passives and actives on substrates, 3D System in Packaging, etc.
• TSV/Wafer Level Packaging: Wafer level packaging, embedded chip packaging, 3D integration, TSV, Silicon interposer, RDL, bumping technologies, etc.
• Interconnection Technologies: Wire-bond technology, Flip-chip technology, solder alternatives (ICP, ACP, ACF, NCP), die attachment (Pb-free), etc.
• Emerging Technologies: Packaging technologies for MEMS, biomedical, optoelectronics, photo voltaic, printed electronics, wearable electronics, etc.
• Materials & Processes: Materials and processes for traditional and advanced microelectronic systems, MEMS, solar, green and biomedical packaging.
• Electrical Modeling & Simulations: Power plane modeling, signal integrity analysis of substrate/package.
• Mechanical Modeling & Simulations: Thermo-mechanical, moisture, fracture, fatigue, vibration, and drop impact modeling, Chip-package interaction, etc.
• Thermal Characterization & Cooling Solutions: Thermal modeling and simulation, component and system level thermal management and characterization
• Quality & Reliability: Component, board and system level reliability assessment, Interfacial adhesion, accelerated testing, failure characterization, etc.
• Wafer/Package Testing & Characterization: High-speed test architectures and systems design, test methodologies, probe card design, package-test interaction, high-throughput testing etc.