The talk will focus on packaging requirements for high bandwidth data processing for compute and communication applications emerging in the next decade. Current trends in packaging architectures to keep the pace of Moore’s law will be discussed. The need to maintain flexibility in product design with late binding architectures and standard physical and electrical interfaces will be highlighted. The complex challenges to serving low cost, high performance and high reliability within a common framework will also be noted.
Dr.Ram Viswanath is the Vice President in TMG and Director of Architecture and Pathfinding for Microelectronics Packaging at Intel. His team is responsible for package technology roadmap and innovations for Client, Server, Handheld, Programmable, Graphics and Communication Processors. He has numerous patents in the area of microelectronics package architecture, package construction, heat transfer and testability of processors. He has authored book chapters and numerous technical papers in conferences, IEEE journals and the prestigious Intel Technology Journal. Ram has a Ph.D in Mechanical and Aerospace Engineering from Rutgers University.
Keynote 2 : Enabling the Building Blocks for Next Generation of Electronics Packaging
For over five decades, transistor has continued to shrink according to Moore’s Law in meeting the insatiable demand for higher computing power. However, substrate/package technology as well as other silicon devices such as RF, power, passives, and sensors do not scale as aggressively, necessitating More-than-Moore approach. Therefore, a new playbook is needed to continue driving Power, Performance and Area Cost improvements. In this regard, one key enabler for heterogeneous integration is advanced packaging, with its four building blocks: RDL, Bump, TSV, and hybrid bonding.
Integration of these packaging schemes, however, comes with a set of challenges, such as step height, warpage, chip-package interaction, interface control, bump coplanarity, bonding temperature, and TSV integration. To address these challenges, Applied Materials has been developing solutions, such as polymer CMP, warpage management, interface engineering, novel electroplating technology, dielectric engineering, and high-aspect ratio TSV gapfill integration.
From a futuristic perspective, Applied envisions that new equipment development must go hand-in-hand with design and layout requirements. This is to enable a new set of design rules, which would allow design companies to achieve performance not achievable with today's WLP equipment-set. Applied is actively engaged in an equipment-focused Design Technology Co-Optimization (DTCO) effort to realize this paradigm shift.
Mr. Glen Mori heads up technology for advanced wafer-level
packaging and through-silicon vias at Applied Materials, including management
of the Applied Packaging Development Center in Singapore. With close to 25 years at Applied, Mr. Mori
has held previous positions with Metal Deposition, Advanced Lithography,
Electrochemical Deposition, and PVD product groups. Mr. Mori holds a BS in Engineering from
University of Illinois at Urbana-Champaign, and a Master’s degree in Science
& Technology from Oregon Health & Science University.
Vice President, Intel
Mr. Glen Mori
Managing Director, Applied Materials